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ST22N144 Просмотр технического описания (PDF) - STMicroelectronics

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ST22N144 Datasheet PDF : 7 Pages
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ST22N144
DESCRIPTION
The ST22N144 is a member of the SmartJplat-
form using a 32-bit Reduced Instruction Set Com-
puter (RISC) core to execute both Native RISC
instructions and JavaCard2.x Technology in-
struction (byte codes) directly (See Figure 2.
"SmartJPlatform EEPROM Architecture", on
page 3).
Direct JavaCardbyte code execution provides
high performance advantage over processors that
emulate the JavaCardbyte code instruction set.
The product features a 24-bit wide linear address-
ing capability and includes User ROM, User RAM,
and User EEPROM.
Memory and Peripheral accesses are controlled
by a Memory Protection Unit that allows to imple-
ment firewalls between applications.
Memories are accessed via two different buses,
allowing simultaneous accesses to code and data.
Memory load and stores can be performed at byte,
short (2-bytes), or word (4-bytes) granularity, with
optional pointer auto increment.
The ST22 core includes dedicated instructions to
accelerate performances of the following algoriths:
DES and Triple DES
Modular Arithmetic on big numbers,
Characteristic two field arithmetic to support
efficiently Elliptic Curves,
CRC 16-bit ISO 3309.
The product has clock and power management,
2 User configurable Timers, a Central Interrupt
Controller and a Random Number Generator.
Figure 2. SmartJ™ Platform EEPROM Architecture
POWER MANAGEMENT
32-bit
RISC
CORE
MPU
RAM
PERIPHERALS
BUS 1
BUS 2
ISO
7816
CLOCK MANAGEMENT
ROM
EEPROM
3/7

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