SST89E52RC Просмотр технического описания (PDF) - Silicon Storage Technology

Номер в каталоге

Компоненты Описание

Список матч

SST89E52RC

FlashFlex MCU

Silicon Storage Technology 

FlashFlex MCU

SST89E52RC / SST89E54RC

3.0 MEMORY ORGANIZATION

The device has separate address spaces for program and

data memory.

3.1 Program Flash Memory

There are two internal flash memory partitions in the

device. The primary flash memory partition (Partition 0) has

16/8 KByte. The secondary flash memory partition (Parti-

tion 1) has 1 KByte. The total flash memory space of both

partitions can be used as a contiguous code storage.

The 16K/8K x8 primary flash partition is organized as 128/

64 sectors, each sector consists of 128 Bytes. The primary

partition is divided into four logical pages as shown in Fig-

ure 3-2

The 1K x8 secondary flash partition is organized as 8 sec-

tors, each sector consists also of 128 Bytes.

For both partitions, the 7 least significant program address

bits select the byte within the sector. The remainder of the

program address bits select the sector within the partition.

3.2 Data RAM Memory

The data RAM has 512 Bytes of internal memory. The first

256 Bytes are available by default. The second 256 Bytes

are enabled by clearing the EXTRAM bit in the AUXR reg-

ister. The RAM can be addressed up to 64 KByte for exter-

nal data memory.

3.3 Expanded Data RAM Addressing

The SST89E5xRC have the capability of 512 Bytes of

RAM. See Figure 3-1.

The device has four sections of internal data memory:

1. The lower 128 Bytes of RAM (00H to 7FH) are

directly and indirectly addressable.

2. The higher 128 Bytes of RAM (80H to FFH) are

indirectly addressable.

3. The special function registers (80H to FFH) are

directly addressable only.

4. The expanded RAM of 256 Bytes (00H to FFH) is

indirectly addressable by the move external

instruction (MOVX) and clearing the EXTRAM bit.

(See “Auxiliary Register (AUXR)” in Section 3.5,

“Special Function Registers”)

Since the upper 128 bytes occupy the same addresses as

the SFRs, the RAM must be accessed indirectly. The RAM

and SFRs space are physically separate even though they

have the same addresses.

Data Sheet

When instructions access addresses in the upper 128

bytes (above 7FH), the MCU determines whether to

access the SFRs or RAM by the type of instruction given. If

it is indirect, then RAM is accessed. If it is direct, then an

SFR is accessed. See the examples below.

Indirect Access:

MOV @R0, #data ; R0 contains 90H

Register R0 points to 90H which is located in the upper

address range. Data in “#data” is written to RAM location

90H rather than port 1.

Direct Access:

MOV 90H, #data

; write data to P1

Data in “#data” is written to port 1. Instructions that write

directly to the address write to the SFRs.

To access the expanded RAM, the EXTRAM bit must be

cleared and MOVX instructions must be used. The extra

256 Bytes of memory is physically located on the chip and

logically occupies the first 256 bytes of external memory

(addresses 000H to FFH).

When EXTRAM = 0, the expanded RAM is indirectly

addressed using the MOVX instruction in combination

with any of the registers R0, R1 of the selected bank or

DPTR. Accessing the expanded RAM does not affect

ports P0, P3.6 (WR#), P3.7 (RD#), or P2. With

EXTRAM = 0, the expanded RAM can be accessed as

in the following example.

Expanded RAM Access (Indirect Addressing only):

MOVX @DPTR, A

; DPTR contains 0A0H

DPTR points to 0A0H and data in “A” is written to address

0A0H of the expanded RAM rather than external memory.

Access to external memory higher than FFH using the

MOVX instruction will access external memory (0100H to

FFFFH) and will perform in the same way as the standard

8051, with P0 and P2 as data/address bus, and P3.6 and

P3.7 as write and read timing signals.

When EXTRAM = 1, MOVX @Ri and MOVX @DPTR will

be similar to the standard 8051. Using MOVX @Ri pro-

vides an 8-bit address with multiplexed data on Port 0.

Other output port pins can be used to output higher order

address bits. This provides external paging capabilities.

Using MOVX @DPTR generates a 16-bit address. This

allows external addressing up the 64K. Port 2 provides the

high-order eight address bits (DPH), and Port 0 multiplexes

the low order eight address bits (DPL) with data. Both

MOVX @Ri and MOVX @DPTR generates the necessary

©2007 Silicon Storage Technology, Inc.

9

S71259-04-000

1/07

Share Link: