IDT723612L30PQF Просмотр технического описания (PDF) - Integrated Device Technology
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IDT723612L30PQF Datasheet PDF : 25 Pages
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IDT723612
CMOS SYNCBiFIFOTM 64 x 36 x 2
PIN DESCRIPTION
Symbol
A0-A35
AEA
Name
Port-A Data
Almost-Empty Flag
AEB
AFA
AFB
B0-B35
CLKA
Port-B Almost-Empty
Flag
Port-A Almost-Full
Flag
Port-B Almost-Empty
Flag
Port-B Data.
Port-A Clock
I/O
I/O
O
(Port A)
O
(Port B)
O
(Port A)
O
(Port B)
I/O
I
CLKB
Port-B Clock
I
CSA
Port-A Chip Select
I
CSB
Port-B Chip Select
I
EFA
Port-A Empty Flag
O
(Port A)
EFB
Port-B Empty Flag
O
(Port B)
ENA
Port-A Enable
ENB
Port-B Enable
FFA
Port-A Full Flag
FFB
Port-B Full Flag
FS1, FS0 Flag-OffsetSelects
MBA
Port-A Mailbox
Select
MBB
Port-B Mailbox
Select
MBF1
Mail1 Register Flag
I
I
O
(Port A)
O
(Port B)
I
I
I
O
MBF2
Mail2 Register Flag
O
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
Description
36-bit bidirectional data port for side A.
Programmable Almost-Empty flag synchronized to CLKA. It is LOW when the number of words in
the FIFO2 is less than or equal to the value in the offset register, X.
Programmable Almost-Full flag synchronized to CLKB. It is LOW when the number of words in
FIFO1 is less than or equal to the value in the offset register, X.
Programmable Almost-Full flag synchronized to CLKA. It is LOW when the number of empty
locations in FIFO1 is less than or equal to the value in the offset register, X.
Programmable Almost-Full flag synchronized to CLKB. It is LOW when the number of empty
locations in FIFO2 is less than or equal to the value in the offset register, X.
36-bit bidirectional data port for side B.
CLKA is a continuous clock that synchronizes all data transfers through port-A and can be
asynchronous or coincident to CLKB. EFA, FFA, AFA, and AEA are synchronized to the
LOW-to-HIGH transition of CLKA.
CLKB is a continuous clock that synchronizes all data transfers through port-B and can be
asynchronous or coincident to CLKA. EFB, FFB, AFB, and AEB are synchronized to the LOW-
to-HIGH transition of CLKB.
CSA must be LOW to enable a LOW-to-HIGH transition of CLKA to read or write data on port-A.
The A0-A35 outputs are in the high-impedance state when CSA is HIGH.
B must be LOW to enable a LOW-to-HIGH transition of CLKB to read or write data on port-B.
The B0-B35 outputs are in the high-impedance state when CSB is HIGH.
EFA is synchronized to the LOW-to-HIGH transition of CLKA. When EFA is LOW, FIFO2 is
empty, and reads from its memory are disabled. Data can be read from FIFO2 to the output
register when EFA is HIGH. EFA is forced LOW when the device is reset and is set HIGH by
the second LOW-to-HIGH transition of CLKA after data is loaded into empty FIFO2 memory.
EFB is synchronized to the LOW-to-HIGH transition of CLKB. When EFB is LOW, the FIFO1 is
empty, and reads from its memory are disabled. Data can be read from FIFO1 to the output
register when EFB is HIGH. EFB is forced LOW when the device is reset and is set HIGH by the
second LOW-to-HIGH transition of CLKB after data is loaded into empty FIFO1 memory.
ENA must be HIGH to enable a LOW-to-HIGH transition of CLKA to read or write data on port-A.
ENB must be HIGH to enable a LOW-to-HIGH transition of CLKB to read or write data on port-B.
FFA is synchronized to the LOW-to-HIGH transition of CLKA. When
and writes to its memory are disabled. FFA is forced LOW when the
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HIGH by the second LOW-to-HIGH transition of CLKA after reset.
FFB is synchronized to the LOW-to-HIGH transition of CLKB. When FFB is LOW, FIFO2 is full,
and writes to its memory are disabled. FFB is forced LOW when the device is reset and is set
HIGH by the second LOW-to-HIGH transition of CLKB after reset.
The LOW-to-HIGH transition of RST latches the values of FS0 and FS1, which selects one of four
preset values for the Almost-Full flag and almost-Empty flag.
A HIGH level on MBA chooses a mailbox register for a port-A read or write operation. When the
A0-A35 outputs are active, a HIGH level on MBA selects data from the mail2 register for output, and
a LOW level selects FIFO2 output register data for output.
A HIGH level on MBB chooses a mailbox register for a port-B read or write operation. When the
B0-B35 outputs are active, a HIGH level on MBB selects data from the mail1 register for output, and
a LOW level selects FIFO1 output register data for output.
MBF1 is set LOW by a LOW-to-HIGH transition of CLKA that writes data to the mail1 register.
Writes to the mail1 register are inhibited while MBF1 is set LOW. MBF1 is set HIGH by a LOW-
to-HIGH transition of CLKB when a port-B read is selected and MBB is HIGH. MBF1 is set HIGH
when the device is reset.
MBF2 is set LOW by a LOW-to-HIGH transition of CLKB that writes data to the mail2 register.
Writes to the mail2 register are inhibited while MBF2 is set LOW. MBF2 is set HIGH by a LOW- to-
HIGH transition of CLKA when a port-A read is selected and MBA is HIGH. MBF2 is set HIGH
when the device is reset.
4
FEBRUARY 13, 2009
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