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IDT723612L20PFGI

CMOS SyncBiFIFO™ 64 x 36 x 2

Integrated Device Technology 

IDT723612

CMOS SYNCBiFIFOTM 64 x 36 x 2

CLKA

CSA

W/RA

MBA

ENA

tCLK

tCLKH

tCLKL

LOW

LOW

LOW

tENS2

tENH2

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

EFA

A0 - A35

CLKB

FFB

CSB

HIGH

tA

Previous Word in FIFO2 Output Register

tSKEW1(1)

tCLK

tCLKH

tCLKL

1

LOW

FIFO2 Full

Next Word From FIFO2

2

tWFF

tWFF

W/RB

MBB

HIGH

ENB

B0 - B35

tENS3

tENS2

tENH3

tENH2

tDS

tDH

To FIFO2

3136 drw13

NOTE:

1. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for FFB to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge

and rising CLKB edge is less than tSKEW1, then FFB may transition HIGH one CLKB cycle later than shown.

Figure 10. FFB Flag Timing and First Available Write when FIFO2 is Full

CLKA

ENA

CLKB

AEB

tENS2

tENH2

tSKEW2(1)

1

X Word in FIFO1

2

tPAE

tPAE

(X+1) Words in FIFO1

tENS2

tENH2

ENB

3136 drw14

NOTES:

1. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AEB to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge

and rising CLKB edge is less than tSKEW2, then AEB may transition HIGH one CLKB cycle later than shown.

2. FIFO1 Write (CSA = LOW, W/RA = HIGH, MBA = LOW), FIFO1 read (CSB = LOW, W/RB = LOW, MBB = LOW).

Figure 11. Timing for AEB when FIFO1 is Almost Empty

19

FEBRUARY 13, 2009

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