IDT723612L15PF Просмотр технического описания (PDF) - Integrated Device Technology
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IDT723612L15PF Datasheet PDF : 25 Pages
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IDT723612
CMOS SYNCBiFIFOTM 64 x 36 x 2
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
The setup and hold time constraints to the port clocks for the port Chip Selects
(CSA, CSB) and Write/Read selects (W/RA, W/RB) are only for enabling write
and read operations and are not related to high-impedance control of the data
outputs. If a port enable is LOW during a clock cycle, the port chip select and
write/read select may change states during the setup and hold time window
of the cycle.
SYNCHRONIZED FIFO FLAGS
Each FIFO is synchronized to its port clock through two flip-flop stages. This
is done to improve flag reliability by reducing the probability of metastable
events on the output when CLKA and CLKB operate asynchronously to one
another. EFA, AEA, FFA, and AFA are synchronized by CLKA. EFB, AEB,
FFB, and AFB are synchronized to CLKB. Tables 4 and 5 show the relationship
of each port flag to FIFO1 and FIFO2.
Each time a word is written to a FIFO, the write pointer is incremented. The
state machine that controls a Full Flag monitors a write-pointer and read pointer
comparator that indicates when the FIFO SRAM status is full, full-1, or full-2.
From the time a word is read from a FIFO, the previous memory location is
ready to be written in a minimum of three cycles of the Full Flag synchronizing
clock. Therefore, a Full Flag is LOW if less than two cycles of the Full Flag
synchronizing clock have elapsed since the next memory write location has
been read. The second LOW-to-HIGH transition on the Full Flag synchroni-
zation clock after the read sets the Full Flag HIGH and the data can be written
in the following clock cycle.
A LOW-to-HIGH transition on a Full Flag synchronizing clock begins the
first synchronization cycle of a read if the clock transition occurs at time tSKEW1
or greater after the read. Otherwise, the subsequent clock cycle can be the first
synchronization cycle.
EMPTY FLAGS (EFA, EFB)
The Empty Flag of a FIFO is synchronized to the port clock that reads
data from its array. When the Empty Flag is HIGH, new data can be read to
the FIFO output register. When the Empty Flag is LOW, the FIFO is empty and
attempted FIFO reads are ignored.
The read pointer of a FIFO is incremented each time a new word is
clocked to the output register. The state machine that controls an Empty Flag
monitors a write-pointer and read-pointer comparator that indicates when the
FIFO SRAM status is empty, empty+1, or empty+2. A word written to a FIFO
can be read to the FIFO output register in a minimum of three cycles of the Empty
Flag synchronizing clock. Therefore, an Empty Flag is LOW if a word in memory
is the next data to be sent to the FIFO output register and two cycles of the port
clock that reads data from the FIFO have not elapsed since the time the word
was written. The Empty Flag of the FIFO is set HIGH by the second LOW-to-
HIGH transition of the synchronizing clock, and the new data word can be read
to the FIFO output register in the following cycle.
A LOW-to-HIGH transition on an Empty Flag synchronizing clock begins the
first synchronization cycle of a write if the clock transition occurs at time tSKEW1
or greater after the write. Otherwise, the subsequent clock cycle can be the first
synchronization cycle.
ALMOST EMPTY FLAGS (AEA, AEB)
The Almost-Empty flag of a FIFO is synchronized to the port clock that
reads data from its array. The state machine that controls an Almost-Empty flag
monitors a write-pointer comparator that indicates when the FIFO SRAM status
is almost-empty, almost-empty+1, or almost-empty+2. The almost-empty state
is defined by the value of the Almost-Full and Almost-Empty Offset register (X).
This register is loaded with one of four preset values during a device reset (see
Reset above). An Almost-Empty flag is LOW when the FIFO contains X or less
words in memory and is HIGH when the FIFO contains (X+1) or more words.
Two LOW-to-HIGH transitions of the Almost-Empty flag synchronizing clocks
are required after a FIFO write for the Almost-Empty flag to reflect the new level
of fill. Therefore, the Almost-Empty flag of a FIFO containing (X+1) or more
words remains LOW if two cycles of the synchronizing clock have not elapsed
since the write that filled the memory to the (X+1) level. An Almost-Empty flag
is set HIGH by the second LOW-to-HIGH transition of the synchronizing clock
after the FIFO write that fills memory to the (X+1) level. A LOW-to-HIGH
transition of an Almost-Empty flag synchronizing clock begins the first synchro-
nization cycle if it occurs at time tSKEW2 or greater after the write that fills the FIFO
to (X+1) words. Otherwise, the subsequent synchronizing clock cycle can be
the first synchronization cycle (see Figure 7 and 8).
FULL FLAG (FFA, FFB)
The Full Flag of a FIFO is synchronized to the port clock that writes data to
its array. When the Full Flag is HIGH, a memory location is free in the SRAM
to receive new data. No memory locations are free when the Full Flag is LOW
and attempted writes to the FIFO are ignored.
ALMOST FULL FLAGS (AFA, AFB)
The Almost-Full flag of a FIFO is synchronized to the port clock that writes
data to its array. The state machine that controls an Almost-Full flag monitors
a write-pointer and read-pointer comparator that indicates when the FIFO
TABLE 4 — FIFO1 FLAG OPERATION
Number of Words
in the FIFO1(1)
Synchronized
to CLKB
EFB AEB
Synchronized
to CLKA
AFA FFA
0
L
L
H
H
1 to X
H
L
H
H
(X+1) to [64–(X+1)]
H
H
H
H
(64–X) to 63
H
H
L
H
64
H
H
L
L
NOTE:
1. X is the value in the Almost-Empty flag and Almost-Full flag offset register.
TABLE 5 — FIFO2 FLAG OPERATION
Number of Words
in the FIFO1(1)
0
1 to X
(X+1) to [64–(X+1)]
(64–X) to 63
64
Synchronized
to CLKB
EFA AEA
L
L
H
L
H
H
H
H
H
H
Synchronized
to CLKA
AFB FFB
H
H
H
H
H
H
L
H
L
L
11
FEBRUARY 13, 2009
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