IDT723612 BiCMOS SyncBiFIFO™
64 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER RECOMMENDED RANGES OF SUPPLY VOLTAGE
AND OPERATING FREE-AIR TEMPERATURE
IDT723612L15 IDT723612L20 IDT723612L30
Symbol
Parameter
Min. Max. Min. Max. Min. Max.
fS
Clock Frequency, CLKA or CLKB
– 66.7 –
50
– 33.4
tCLK
Clock Cycle Time, CLKA or CLKB
15
–
20
–
30
–
tCLKH Pulse Duration, CLKA and CLKB HIGH
6
–
8
–
12
–
tCLKL Pulse Duration, CLKA and CLKB LOW
6
–
8
–
12
–
tDS
Setup Time, A0-A35 before CLKA↑ and B0-B35 4
–
5
–
6
–
before CLKB↑
tENS1 Setup Time, CSA, W/RA before CLKA↑; CSB,
6
–
6
–
7
–
W/RB before CLKB↑
tENS2 Setup Time, ENA, before CLKA↑; ENB before
4
–
5
–
6
–
CLKB↑
tENS3 Setup Time, MBA before CLKA↑: MBB before
4
–
5
–
6
–
CLKB↑
tPGS
Setup Time, ODD/EVEN and PGA before
4
–
5
–
6
–
CLKA↑; ODD/EVEN and PGB before CLKB↑(1)
tRSTS
Setup Time, RST LOW before CLKA↑
or CLKB↑(2)
5
–
6
–
7
–
tFSS
Setup Time, FS0/FS1 before RST HIGH
5
–
6
–
7
–
tDH
tENH1
Hold Time, A0-A35 after CLKA↑ and B0-B35
after CLKB↑
Hold Time, CSA W/RA after CLKA↑; CSB,
W/RB after CLKB↑
2.5
–
2.5
–
2.5
–
2
–
2
–
2
–
tENH2 Hold Time, ENA, after CLKA↑; ENB after CLKB↑ 2.5
–
2.5
–
2.5
–
tENH3 Hold Time, MBA after CLKA↑; MBB after CLKB↑ 1
–
1
–
1
–
tPGH
Hold Time, ODD/EVEN and PGA after CLKA↑;
1
–
1
–
1
–
ODD/EVEN and PGB after CLKB↑(1)
tRSTH Hold Time, RST LOW after CLKA↑ or CLKB↑(2)
5
–
6
–
7
–
tFSH
Hold Time, FS0 and FS1 after RST HIGH
4
–
4
–
4
–
tSKEW1(3) Skew Time, between CLKA↑ and CLKB↑
for EFA, EFB, FFA, and FFB
8
–
8
–
10
–
tSKEW2(3) Skew Time, between CLKA↑ and CLKB↑
For AEA, AEB, AFA, and AFB
9
–
16
–
20
–
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes:
1. Only applies for a clock edge that does a FIFO read.
2. Requirement to count the clock edge as one of at least four needed to reset a FIFO.
3. Skew time is not a timimg constraint for proper device operation and is only included to illustrate the timing relation-
ship between CLKA cycle and CLKB cycle.
7