IDT723612L15PQF(1997) Просмотр технического описания (PDF) - Integrated Device Technology

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IDT723612L15PQF
(Rev.:1997)

BiCMOS SyncBiFIFO 64 x 36 x 2

Integrated Device Technology 

IDT723612 BiCMOS SyncBiFIFO™

64 x 36 x 2

PIN DESCRIPTION

Symbol

A0-A35

AEA

Name

Port-A Data

Almost-Empty Flag

I/O

I/O

O

(Port A)

AEB Port-B Almost-Empty O

Flag

(PortB)

AFA Port-A Almost-Full O

Flag

(Port A)

AFB Port-B Almost-Empty O

Flag

(Port B)

B0-B35

Port-B Data.

I/O

CLKA

Port-A Clock

I

CLKB

Port-B Clock

I

CSA Port-A Chip Select

I

CSB Port-B Chip Select

I

EFA Port-A Empty Flag O

(Port A)

EFB Port-B Empty Flag O

(Port B)

ENA

ENB

FFA

Port-A Enable

I

Port-B Enable

I

Port-A Full Flag

O

(Port A)

FFB

Port-B Full Flag

O

(Port B)

FS1, FS0 Flag-Offset Selects I

MBA Port-A Mailbox Select I

COMMERCIAL TEMPERATURE RANGE

Description

36-bit bidirectional data port for side A.

Programmable almost-empty flag synchronized to CLKA. It is LOW when

the number of words in the FIFO2 is less than or equal to the value in the

offset register, X.

Programmable almost-full flag synchronized to CLKB. It is LOW when the

number of words in FIFO1 is less than or equal to the value in the

offset register, X.

Programmable almost-full flag synchronized to CLKA. It is LOW when the

number of empty locations in FIFO1 is less than or equal to the value in the

offset register, X.

Programmable almost-full flag synchronized to CLKB. It is LOW when the

number of empty locations in FIFO2 is less than or equal to the value in the

offset register, X.

36-bit bidirectional data port for side B.

CLKA is a continuous clock that synchronizes all data transfers through port-

A and can be aynchronous or coincident to CLKB. EFA, FFA, AFA, and AEA

are synchronized to the LOW-to-HIGH transition of CLKA.

CLKB is a continuous clock that synchronizes all data transfers through port-

B and can be asynchronous or coincident to CLKA. EFB, FFB, AFB, and

AEB are synchronized to the LOW-to-HIGH transition of CLKB.

CSA must be LOW to enable a LOW-to-HIGH transition of CLKA to read or

write data on port-A. The A0-A35 outputs are in the high-impedance state

when CSA is HIGH.

B must be LOW to enable a LOW-to-HIGH transition of CLKB to read or

write data on port-B. The B0-B35 outputs are in the high-impedance state

when CSB is HIGH.

EFA is synchronized to the LOW-to-HIGH transition of CLKA. When EFA is

LOW, FIFO2 is empty, and reads from its memory are disabled. Data can

be read from FIFO2 to the output register when EFA is HIGH. EFA is forced

LOW when the device is reset and is set HIGH by the second LOW-to-HIGH

transition of CLKA after data is loaded into empty FIFO2 memory.

EFB is synchronized to the LOW-to-HIGH transition of CLKB. When EFB is

LOW, the FIFO1 is empty, and reads from its memory are disabled. Data

can be read from FIFO1 to the output register when EFB is HIGH. EFB is

forced LOW when the device is reset and is set HIGH by the second LOW-

to-HIGH transition of CLKB after data is loaded into empty FIFO1 memory.

ENA must be HIGH to enable a LOW-to-HIGH transition of CLKA to read or

write data on port-A.

ENB must be HIGH to enable a LOW-to-HIGH transition of CLKB to read or

write data on port-B.

FFA is synchronized to the LOW-to-HIGH transition of CLKA. When FFA is

LOW, FIFO1 is full, and writes to its memory are disabled. FFA is forced

LOW when the device is reset and is set HIGH by the second LOW-to-HIGH

transition of CLKA after reset.

FFB is synchronized to the LOW-to-HIGH transition of CLKB. When FFB is

LOW, FIFO2 is full, and writes to its memory are disabled. FFB is forced

LOW when the device is reset and is set HIGH by the second LOW-to-HIGH

transition of CLKB after reset.

The LOW-to-HIGH transition of RST latches the values of FS0 and FS1,

which selects one of four preset values for the almost-full flag and almost-

empty flag.

A HIGH level on MBA chooses a mailbox register for a port-A read or write

operation. When the A0-A35 outputs are active, a HIGH level on MBA

selects data from the mail2 register for output, and a LOW level selects

FIFO2 output register data for output.

4

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