IDT723612L20PFI(2002) Просмотр технического описания (PDF) - Integrated Device Technology

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IDT723612L20PFI
(Rev.:2002)

CMOS SyncBiFIFOTM 64 x 36 x 2

Integrated Device Technology 

IDT723612

CMOS SYNCBiFIFOTM 64 x 36 x 2

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

CLKB

CSB LOW

tCLK

tCLKH tCLKL

W/RB HIGH tENS3

MBB

ENB

tENS2

tENH3

tENH2

FFB HIGH tDS

tDH

B0 - B35

CLKA

EFA

W1

(1)

tSKEW1

tCLK

tCLKH tCLKL

1

FIFO2 Empty

2

tREF

tREF

CSA LOW

W/RA LOW

MBA LOW

ENA

A0 -A35

tENS2

tENH2

tA

W1

3136 drw11

NOTE:

1. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for EFA to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge

and rising CLKA edge is less than tSKEW1, then the transition of EFA HIGH may occur one CLKA cycle later than shown.

Figure 8. EFA Flag Timing and First Data Read when FIFO2 is Empty

17

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