IDT723612L15PQFI(2002) Просмотр технического описания (PDF) - Integrated Device Technology
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IDT723612L15PQFI Datasheet PDF : 25 Pages
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IDT723612
CMOS SYNCBiFIFOTM 64 x 36 x 2
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
SRAM status is almost-full, almost-full-1, or almost-full-2. The almost-full state
is defined by the value of the Almost-Full and Almost-Empty Offset register (X).
This register is loaded with one of four preset values during a device reset (see
Reset above). An Almost-Full flag is LOW when the FIFO contains (64-X) or
more words in memory and is HIGH when the FIFO contains [64-(X+1)] or
less words.
Two LOW-to-HIGH transitions of the Almost-Full flag synchronizing clock are
required after a FIFO read for the Almost-Full flag to reflect the new level of fill.
Therefore, the Almost-Full flag of a FIFO containing [64-(X+1)] or less words
remains LOW if two cycles of the synchronizing clock have not elapsed since
the read that reduced the number of words in memory to [64-(X+1)]. An Almost-
Full flag is set HIGH by the second LOW-to-HIGH transition of the synchronizing
clock after the FIFO read that reduces the number of words in memory to [64-
(X+1)]. A second LOW-to-HIGH transition of an Almost-Full flag synchronizing
clock begins the first synchronization cycle if it occurs at time tSKEW2 or greater
after the read that reduces the number of words in memory to [64-(X+1)].
Otherwise, the subsequent synchronizing clock cycle can be the first synchro-
nization cycle (see Figure 14 and 15).
MAILBOX REGISTERS
Each FIFO has a 36-bit bypass register to pass command and control
information between port A and port B without putting it in queue. The Mailbox
select (MBA, MBB) inputs choose between a mail register and a FIFO for a
port data transfer operation. A LOW-to-HIGH transition on CLKA writes A0-
A35 data to the mail1 register when a port-A write is selected by CSA, W/RA,
and ENA and MBA HIGH. A LOW-to-HIGH transition on CLKB writes B0-B35
data to the mail2 register when a port-B write is selected by CSB, W/RB, and
ENB and MBB is HIGH. Writing data to a mail register sets the corresponding
flag (MBF1 or MBF2) LOW. Attempted writes to a mail register are ignored while
the mail flag is LOW.
When a port's data outputs are active, the data on the bus comes from the
FIFO output register when the port Mailbox-select input (MBA, MBB) is LOW
and from the mail register when the port mailbox-select input is HIGH. The Mail1
register Flag (MBF1) is set HIGH by a LOW-to-HIGH transition on CLKB when
a port-B read is selected by CSB, W/RB, and ENB and MBB is HIGH. The Mail2
register Flag (MBF2) is set HIGH by a LOW-to-HIGH transition on CLKA when
port-A read is selected by CSA, W/RA, and ENA and MBA is HIGH. The data
in a mail register remains intact after it is read and changes only when new data
is written to the register.
PARITY CHECKING
The port-A inputs (A0-A35) and port-B inputs (B0-B35) each have four
parity trees to check the parity of incoming (or outgoing) data. A parity failure
on one or more bytes of the input bus is reported by a LOW level on the port
Parity Error Flag (PEFA, PEFB). Odd or even parity checking can be selected,
and the Parity Error Fags can be ignored if this feature is not desired.
Parity status is checked on each input bus according to the level of the Odd/
Even parity (ODD/EVEN) select input. A parity error on one or more bytes of
a port is reported by a LOW level on the corresponding port Parity Error Flag
(PEFA, PEFB) output. Port-A bytes are arranged as A0-A8, A9-A17, A18-
A26, and A27-A35 with the most significant bit of each byte used as the parity
bit. Port-B bytes are arranged as B0-B8, B9-B17, B18-B26, and B27-B35,
with the most significant bit of each byte used as the parity bit. When odd/even
parity is selected, a port parity error flag (PEFA, PEFB) is LOW if any byte on
the port has an odd/even number of LOW levels applied to the bits.
The four parity trees used to check the A0-A35 inputs are shared by the mail2
register when parity generation is selected for port-A reads (PGA = HIGH).
When a port-A read from the mail2 register with parity generation is selected
with W/RA LOW, CSA LOW, ENA HIGH, MBA HIGH, and PGA HIGH, the port-
A Parity Error Flag (PEFA) is held HIGH regardless of the levels applied to
the A0-A35 inputs. Likewise, the parity trees used to check the B0-B35 inputs
are shared by the mail1 register when parity generation is selected for port-
B reads (PGB = HIGH). When a port-B read from the mail1 register with parity
generation is selected with W/RB LOW, CSB LOW, ENB HIGH, MBB HIGH,
and PGB HIGH, the port-B parity error flag (PEFB) is held HIGH regardless
of the levels applied to the B0-B35 inputs.
PARITY GENERATION
A HIGH level on the port-A Parity Generate select (PGA) or port-B Parity
Generate select (PGB) enables the IDT723612 to generate parity bits for
port reads from a FIFO or mailbox register. Port-A bytes are arranged as A0-
A8, A9-A17, A18-26, and A27-A35, with the most significant bit of each byte
used as the parity bit. Port-B bytes are arranged as B0-B8, B9-B17, B18-B26,
and B27-B35, with the most significant bit of each byte used as the parity bit.
A write to a FIFO or mail register stores the levels applied to all thirty-six inputs
regardless of the state of the Parity Generate select (PGA, PGB) inputs. When
data is read from a port with parity generation selected, the lower eight bits of
each byte are used to generate a parity bit according to the level on the ODD/
EVEN select. The generated parity bits are substituted for the levels originally
written to the most significant bits of each byte as the word is read to the data
outputs.
Parity bits for FIFO data are generated after the data is read from SRAM
and before the data is written to the output register. Therefore, the port-A parity
generate select (PGA) and Odd/Even parity select (ODD/EVEN) have setup
and hold time constraints to the port-A Clock (CLKA) and the port-B Parity
Generate select (PGB) and ODD/EVEN have setup and hold-time constraints
to the port-B Clock (CLKB). These timing constraints only apply for a rising clock
edge used to read a new word to the FIFO output register.
The circuit used to generate parity for the mail1 data is shared by the port-
B bus (B0-B35) to check parity and the circuit used to generate parity for the
mail2 data is shared by the port-A bus (A0-A35) to check parity. The shared
parity trees of a port are used to generate parity bits for the data in a mail register
when the port Write/Read select (W/RA, W/RB) input is LOW, the port mail select
(MBA, MBB) input is HIGH, Chip Select (CSA, CSB) is LOW, Enable (ENA,
ENB) is HIGH, and port Parity Generate select (PGA, PGB) is HIGH.
Generating parity for mail register data does not change the contents of the
register.
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