IDT723612L30PQF(1997) Просмотр технического описания (PDF) - Integrated Device Technology

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IDT723612L30PQF
(Rev.:1997)

BiCMOS SyncBiFIFO 64 x 36 x 2

Integrated Device Technology 

IDT723612 BiCMOS SyncBiFIFO™

64 x 36 x 2

CLKA

ENA

CLKB

AEB

tENS2

tENH2

(1)

tSKEW2

1

X Word in FIFO1

ENB

COMMERCIAL TEMPERATURE RANGE

2

tPAE

(X+1) Words in FIFO1

tENS2

tPAE

tENH2

3136 drw 13

Notes:

1. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AEB to transition HIGH in the

next CLKB cycle. If the time between the rising CLKA edge and rising CLKB edge is less than tSKEW2, then AEB may

transition HIGH one CLKB cycle later than shown.

2. FIFO1 Write (CSA = LOW, W/RA = HIGH, MBA = LOW), FIFO1 read (CSB = LOW, W/RB = LOW, MBB = LOW).

Figure 10. Timing for AEB when FIFO1 is Almost Empty

CLKB

ENB

CLKA

AEA

tENS2

tENH2

tSKEW2(1)

1

X Words in FIFO2

ENA

2

tPAE

(X+1) Words in FIFO2

tENS2

tPAE

tENH2

3136 drw 14

Notes:

1. tSKEW2 is the minimum time between a rising CLKB edge and a rising CLKA edge for AEA to transition HIGH in the

next CLKA cycle. If the time between the rising CLKB edge and rising CLKA edge is less than tSKEW2, then AEA may

transition HIGH one CLKA cycle later than shown.

2. FIFO2 Write (CSB = LOW, W/RB = HIGH, MBB = LOW), FIFO2 read (CSA = LOW, W/RA = LOW, MBA = LOW).

Figure 11. Timing for AEA when FIFO2 is Almost Empty

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