IDT71B74S20TP Просмотр технического описания (PDF) - Integrated Device Technology
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IDT71B74S20TP Datasheet PDF : 9 Pages
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IDT71B74
BiCMOS STATIC RAM 64K (8K x 8-BIT) CACHE-TAG RAM
COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OF WRITE CYCLE NO. 2 (CS Controlled Timing)(1, 6)
t WC
ADDRESS
OE
t CW (2)
(5)
t WR (3)
CS
t AW
t AS
WE
DATAOUT(7)
DATA IN
t WHZ(8,9)
t OW (9)
t DW
t DH
DATA VALID
3013 drw 12
NOTES:
1. , WE CS must be inactive during all address transitions.
2. A write occurs during the overlap of a LOW WE and a LOW CS.
3. tWR is measured from the earlier of CS or WE going HIGH to the end of the write cycle.
4. During this period, I/O pins are in the output state and input signals must not be applied.
5. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state.
6. OE is continuously HIGH, OE ≥ VIH. If during the WE controlled write cycle the OE is LOW, tWP must be greater or equal to tWHZ + tDW to allow the I/O
drivers to turn off and the data to be placed on the bus for the required tDW. If OE is HIGH during the WE controlled write cycle, this requirement does not
apply and the minimum write pulse is the specified tWP. For a CS controlled write cycle, OE may be LOW with no degradation to tCW timing.
7. DATAOUT is never enabled, therefore the output is in High-Z state during the entire write cycle.
8. tWHZ is not included if OE remains HIGH during the write cycle. If OE is LOW during the Write Enabled write cycle then tWHZ must be added to tWP and tCW.
9. Transition is measured ±200mV from steady state.
AC ELECTRICAL CHARACTERISTICS (VCC = 5.0V ± 10%)
71B74S8 71B74S10 71B74S12 71B74S15 71B74S20
Symbol
Parameter
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
Match Cycle
tADM
Address to MATCH Valid
—
8
— 10 — 12 — 15 — 20 ns
tCSM
tCSMHI(1)
Chip Select to MATCH Valid
Chip Select to MATCH HIGH
—
7
—
7
—
8
— 10 — 10 ns
—
7
—
8
—
8
—
8
—
8
ns
tDAM
tOEMHI(1)
tWEMHI(1)
tRSMHI(1)
Data Input to MATCH Valid
OE LOW to MATCH HIGH
WE LOW to MATCH HIGH
RESET LOW to MATCH HIGH
—
7
—
8
— 10 — 12 — 12 ns
—
7
—
8
— 10 — 10 — 10 ns
—
7
—
8
— 10 — 10 — 10 ns
—
8
— 10 — 10 — 12 — 15 ns
tMHA
MATCH Valid Hold From Address 2
—
2
—
2
—
2
—
2
— ns
tMHD
MATCH Valid Hold From Data
2
—
2
—
2
—
2
—
2
— ns
NOTE:
1. This parameter is guaranteed with the AC Load (Figure 3) by device characterization, but is not production tested.
3013 tbl 12
14.1
7
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