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IDT71B74S12Y

BiCMOS STATIC RAM 64K (8K x 8-BIT) CACHE-TAG RAM

Integrated Device Technology 

IDT71B74

BiCMOS STATIC RAM 64K (8K x 8-BIT) CACHE-TAG RAM

COMMERCIAL TEMPERATURE RANGE

AC ELECTRICAL CHARACTERISTICS (VCC = 5.0V ± 10%)

Symbol

Parameter

71B74S8 71B74S10 71B74S12 71B74S15

Min. Max. Min. Max. Min. Max. Min. Max.

Read Cycle

tRC

Read Cycle Time

8 — 10 — 12 — 15 —

tAA

Address Access Time

—

8

— 10 — 12 — 15

tACS

tCLZ(1)

Chip Select Access Time

Chip Select to Output in Low-Z

—

6

—

7

—

8

—

8

2 — 2— 2 — 3 —

tOE

tOLZ(1)

tCHZ(1)

tOHZ(1)

Output Enable to Output Valid

Output Enable to Output in Low-Z

Chip Select to Output in High-Z

Output Disable to Output in High-Z

—

5

—

6

—

6

—

8

2 — 2— 2 — 2 —

—

4

—

5

—

5

—

7

—

4

—

4

—

5

—

5

tOH

Output Hold from Address Change

3 — 3— 3 — 3 —

NOTE:

1. This parameter is guaranteed with the AC Load (Figure 2) by device characterization, but is not production tested.

71B74S20

Min. Max. Unit

20 — ns

— 20 ns

— 10 ns

3

— ns

— 9 ns

2

— ns

— 8 ns

— 8 ns

3

— ns

3013 tbl 10

TIMING WAVEFORM OF READ CYCLE NO. 1(1)

tRC

ADDRESS

tAA

OE

CS

DATAOUT

tOE

tOLZ (5)

tACS (3)

t CLZ (5)

t OH

t OHZ (5)

t CHZ (5)

DATAOUT VALID

TIMING WAVEFORM OF READ CYCLE NO. 2 (1, 2, 4)

tRC

ADDRESS

DATAOUT

tAA

tOH

tOH

DATAOUT VALID

NOTES:

1. WE is HIGH for Read cycle.

2. Device is continuously selected, CS is LOW.

3. Address valid prior to or coincident with CS transition LOW; otherwise tAA is the limiting parameter.

4. OE is continuously active, OE is LOW.

5. Transition is measured ±200mV from steady state.

3013 drw 09

3013 drw 10

14.1

5

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