SPT7862 Просмотр технического описания (PDF) - Cadeka Microcircuits LLC.
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SPT7862 Datasheet PDF : 10 Pages
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Figure 2 – Typical Interface Circuit
Ref In (+4V)
VINA
ClockINA
Ref In (+4V)
VINB
ClockINB
VRHFA
VRHSA
VRLSA
VRLFA
VINA
VINRA
CLKA
VCAL
SPT7862
OVDDA +3V/5V
DA9–0 10
OGNDA
DAVA
VRHFB
VRHSB
VRLSB
VRLFB
VINB
VINRB
CLKB
AVDD AGND
OVDDB +3V/5V
DB9–0 10
OGNDB
DAVB
EN
DGND* DVDD
Enable/Tri-State
(Enable = Active Low)
+D5V
Interface
Logic
Interface
Logic
+A5
+D5V
FB
+A5
+
10 µF
+5V
Analog
+5V
Analog
Return
+D5
*To reduce the possibility of latch-up, avoid connecting
the DGND pins of the ADC to the digital ground of the system.
NOTES: 1. FB is a 10 µH inductor or ferrite bead. It is
+
10 µF
to be located as close to the device as possible.
2.
All capacitors are 0.1
otherwise specified.
µF
surface-mount,
unless
+5V
Digital
+5V
Digital
Return
TYPICAL INTERFACE CIRCUIT
Very few external components are required to achieve the
stated device performance. Figure 2 shows the typical inter-
face requirements when using the SPT7862 in normal
circuit operation. The following sections provide descrip-
tions of the major functions and outline critical performance
criteria to consider for achieving the optimal device
performance.
POWER SUPPLIES AND GROUNDING
CADEKA suggests that both the digital and the analog sup-
ply voltages on the SPT7862 be derived from a single ana-
log supply as shown in figure 2. A separate digital supply
should be used for all interface circuitry. CADEKA suggests
using this power supply configuration to prevent a possible
latch-up condition on power up.
OPERATING DESCRIPTION
The general architecture for the dual CMOS ADC is shown
in the block diagram. Each ADC design contains 16 identi-
cal successive approximation (SAR) ADC sections (all oper-
ating in parallel), a 16-phase clock generator, an 11-bit 16:1
digital output multiplexer, correction logic, and a voltage ref-
erence generator which provides common reference levels
for each ADC section.
The high sample rate is achieved by using multiple SAR
ADC sections in parallel, each of which samples the input
signal in sequence. Each SAR ADC uses 16 clock cycles to
complete a conversion. The clock cycles are allocated as
follows:
Table II – Clock Cycles
Clock
1
2
3
4
5–15
16
Operation
Reference zero sampling
Auto-zero comparison
Auto-calibrate comparison
Input sample
11-bit SAR conversion
Data transfer
The 16-phase clock, which is derived from the input clock,
synchronizes these events. The timing signals for adjacent
SAR ADC sections are shifted by one clock cycle so that the
analog input is sampled on every cycle of the input clock by
exactly one SAR ADC section. After 16 clock periods, the
timing cycle repeats. The latency from analog input sample
to the corresponding digital output is 12 clock cycles.
SPT7862
6
2/23/00
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