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AN7820

EVALUATION BOARD

Fairchild Semiconductor 

DYNAMIC TESTING

Figure 16: Dynamic Testing Test Set-up

REF GENERATOR # 1

OUT

IN BPF

HIGH SPEED

MEMORY

REF GENERATOR #2

IN

REF

IN

GENERATOR # 3

P2/P3

DB792

DAC

OUT

CPU / DSP

SCOPE OR

SPECTRUM

ANALYSER

Figure 16 is the recommended block diagram for dynamic

testing of the SPT7820 or SPT7824 using the EB7820/24

evaluation board. In earlier tests, the DAC OUT signal was

used to analyze the ADC’s dynamic performances (SNR and

THD) through a spectrum analyzer. This method of testing

presented some uncertainties. The DAC had to be near

perfect and free from glitches, and its dynamic accuracy

(DLE and ILE) had to be far better than the ADC under test.

Any errors in the DAC wereadded to the total SNR and/or

THD.

Today, it is preferable to perform these tests by means of

digital signal processing (DSP). There are currently numer-

ous standard software packages on the market to service

this application. The EB7820/24 provides the data outputs

through P2. (See table 5 for detail.) The reconstruction DAC

can be obtained from DB792 daughter board. Both set-ups

are very important in characterizing the dynamic perfor-

mance of the SPT7820 or SPT7824.

In many cases, the speed of the capture memory is much

slower than the available output valid data of the ADC under

test. In this case, it is necessary to decimate the capture

clock at a rate of Fs/N, where N is a power of 2. The beat

frequency can be achieved by slightly changing the analog

input frequency by an amount of ∆fin. For a 4096-point FFT,

the beat frequency of ∆fin = Fc/4096 is added (or subtracted)

to the analog input frequency. 4096 data points are filled in

one test period where the input is at Fin ± (Fc/4096) and the

output is updated at 1/Fc interval. Select Fin as the multiple

(integer) of Fc to achieve a complete system synchroniza-

tion. Both capture memory and the DAC run at a relatively

low update rate (Fs/N).

The daughter board, DB972, is capable of updating to 80

MSPS.

EB7820/24 CALIBRATION

This section is a guide for the DC calibration of the EB7820/

24 if needed. Note that this board was fully calibrated before

shipment. VST and VSB voltages require new calibration on

each new SPT7820 or 7824.

Check for installation of jumpers SJ2B, SJ2C and SJ3.

1.0 Equipment Needed

1.1 Four DC power supplies: analog +5 V, analog -5.2 V,

digital +5 V and digital -5.2 V.

1.2 One Hewlett Packard, HP3325A, function generator or

equivalent.

1.3 One DVM with 5 and 1/2 digit precision.

1.4 One Oscilloscope.

2.0 Equipment Set-Up / Hook-Up

2.1 Ensure that socket U1 does not haveSPT7820 or

SPT7824 in it.

2.2 Connect all four power supplies as shown in table 1,

and figures 2 and figure 3.

2.3 Connect the function generator to CLK BNC.

2.4 Set the CLK to 3 MHz, sine wave , ±2 V.

2.5 Connect VIN to AGND.

3.0 References Calibration

3.1 Monitor TP1 with respect to AGND test point with DVM.

3.2 Adjust R1 for +2.500 V at TP1.

3.3 Monitor TP2 with respect to AGND test point with DVM.

3.4 Adjust R2 for -2.500 V at TP2.

3.5 Turn all power to off.

3.6 Install SPT7820 or SPT7824 into U1 socket. (Fepeat

from this procedure for all new devices.)

3.7 Turn all power back to on.

3.8 Monitor U1, pin 22 (VST) with respect to AGND test

point with DVM.

3.9 Adjust R1 for +2.000 V at VST.

3.10 Monitor U1, pin 27 (VSB) with respect to AGND test

point with DVM.

3.11 Adjust R2 for -2.000 V at VSB.

3.12 Repeat the procedure from paragraph 3.8 until VST

and VSB reach the desired voltages (±2.000 V respec-

tively).

4.0 Clock Circuit Calibration

4.1 Monitor PJ1 with scope on channel 1 (externally sync

to the generator).

4.2 Observe the TTL clock and adjust R3 for approximately

50% of duty cycle.

5.0 Latches (U7 and U8) Test

5.1 Remove R10.

5.2 Connect VIN to TP1.

5.3 Monitor P2, odd number pins (7-25), with scope and

observe TTL-logic high on all pins.

5.4 Connect VIN to TP2 .

5.5 Monitor P2, odd number pins (7-25), with scope and

observe TTL logic low on all pins.

End of calibration Procedure

AN7820/24

12

5/22/97

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