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SP8660 Просмотр технического описания (PDF) - Zarlink Semiconductor Inc

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SP8660
ZARLINK
Zarlink Semiconductor Inc ZARLINK
SP8660 Datasheet PDF : 5 Pages
1 2 3 4 5
OPERATING NOTES
1.The clock inputs (pins 1 and 8) should be capacitively coupled
to the signal source. When driven single ended, the input signal
path is completed by a capacitor from the unused input to ground.
2. In the absence of a signal the devices will self-oscillate. This can
be prevented by connecting a 39kresistor from either input to
ground. If the device is driven single ended, it is recommended
that the pull-down resistor be connected to the decoupled unused
input. There will be a loss in sensitivity of approximately 200mV.
3. The device will operate down to DC but input slew rate must be
better than 100V/µs.
4. The open collector output will drive three TTL loads, and
therefore requires a a suitable resistor to VCC to maintain noise
immunity. In order to maintain noise immunity on transitions, this
SP8660
resistor should not exceed 4·7k. For interfacing to CMOS, the
open collector may be restored to a 110V line via a 3·3kresistor.
The output sink current must not exceed 10mA and the use of too
low a value of resistor may lead to a loss of noise immunity,
especially at low temperatures.
5. Input impedance varies as a function of frequency; see Fig. 4.
6. The rise time of the open collector output waveform is directly
proportional to the load capacitance and load resistor value.
Therefore, the load capacitance should be minimised and the
load resistor kept to a minimum compatible with system power
requirements.
In the test configuration of Fig. 5, the output rise time is
approximately 20ns and the fall time is typically 10ns.
FROM
GENERATOR
TO SAMPLING
SCOPE
1n
1
INPUT
8
39k 1n
VCC
10n
1n
2
1
DUT
4
8
5
1n
110V
3·3k
1k 100n
7p
SAMPLING
SCOPE
INPUT
Fig. 5 Test circuit
15V
1n
2
DIVIDE BY
10
1·6k
1·6k
15V/110V (DEPENDING ON
CMOS SUPPLY VOLTAGE)
3·3k
4
CMOS
BIAS
5
Fig. 6. Typical application circuit showing interfacing
15V
2·2k
2
SP8660 4
TTL
Fig. 7. Interfacing to TTL. Load not to exceed 3 TTL unit loads
3

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