SP674AB Просмотр технического описания (PDF) - Signal Processing Technologies
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SP674AB Datasheet PDF : 14 Pages
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OUTPUT BITS
2
12/8
3
CS
A0 4
R/C 5
CE 6
MSB 27 26 25 24 23 22 21 20 19 18 17 16 LSB
CONTROL
LOGIC
NIBBLE A
NIBBLE B
NIBBLE C
THREE–STATE BUFFERS AND CONTROL
12–BITS
-15V
R1
100K
+15V
100K
0 TO 10V
10V
IN
13
ANALOG
INPUTS
20V
IN 14
0 TO 20V
BIP
OFF 12
100Ω
OSCILLATOR
12–BITS
SAMPLE/HOLD
MSB
12–BIT SAR
STROBE
CDAC
LSB
COMP
28
STS
+5V
1 VLOGIC
1µF
15 DGND
VREF
OUT 8
REF
AMP
R2
100Ω
10
VREF
IN
VCC 7
1µF
+15V
9
AGND
Figure 4. Unipolar Input Connections
REF
OFFSET/GAIN
TRIM NETWORK
11
NO CONNNECTION
PERMITTED
and digital sections), and grounding. Digital
timing, calibration and the analog signal source
must be considered for correct operation.
To achieve specified accuracy, a double–sided
printed circuit board with a copper ground plane
on the component side is recommended. Keep
analog signal traces away from digital lines. It is
best to lay the PC board out such that there is an
analog section and a digital section with a single
point ground connection between the two through
an RF bead. If this is not possible, run analog
OUTPUT BITS
2
12/8
3
CS
A0 4
R/C 5
CE 6
MSB 27 26 25 24 23 22 21 20 19 18 17 16 LSB
CONTROL
LOGIC
NIBBLE A
NIBBLE B
NIBBLE C
THREE–STATE BUFFERS AND CONTROL
12–BITS
OSCILLATOR
12–BIT SAR
ANALOG
INPUTS
±5V
±10V
10V
IN 13
20V
IN 14
BIP
OFF 12
12–BITS
SAMPLE/HOLD
MSB
STROBE
CDAC
LSB
COMP
28
STS
+5V
1 VLOGIC
1µF
15 DGND
100Ω
R1
VREF
OUT 8
REF
AMP
REF
OFFSET/GAIN
TRIM NETWORK
100Ω
R2
10
VREF
IN
VCC 7
1µF
+15V
9
AGND
11
NO CONNECTION
PERMITTED
Figure 5. Bipolar Input Connections
9
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