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SP6132EB

Evaluation Board Manual

Signal Processing Technologies 

LOOP COMPENSATION DESIGN

The open loop gain of the SP6132EB can be divided into the gain of the error

amplifier Gamp(s), PWM modulator Gpwm, buck converter output stage Gout(s), and

feedback resistor divider Gfbk. In order to crossover at the selecting frequency fco, the

gain of the error amplifier has to compensate for the attenuation caused by the rest of

the loop at this frequency. The goal of loop compensation is to manipulate the open

loop frequency response such that its gain crosses over 0dB at a slope of –20dB/dec.

The open loop crossover frequency should be higher than the ESR zero of the output

capacitors but less than 1/5 of the switching frequency fs to insure proper operation.

Since the SP6132EB is designed with a Ceramic Type output capacitors, a Type III

compensation circuit is required to give a phase boost of 180° in order to counteract the

effects of the output LC under damped resonance double pole frequency.

Figure 11. SP6132EB Voltage Mode Control Loop with Loop Dynamic

The simple guidelines for positioning the poles and zeros and for calculating the

component values for a Type III compensation are as follows.

a. Choose fco = fs / 5

b. Calculate fp_LC

fp_LC = 1 / 2π [(L) (C)] ^ 1/2

c. Calculate fz_ESR

fz_ESR = 1 / 2π (Resr) (Cout)

d. Select R1 component value such that 50kΩ ≤ R1 ≤ 100kΩ

e. Calculate R2 base on the desired Vout

R2 = R1 / [(Vout / 0.80V) – 1]

6

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