SP3222H Просмотр технического описания (PDF) - Signal Processing Technologies
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SP3222H Datasheet PDF : 17 Pages
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Phase 4: VDD Transfer (Figure 16)
The fourth phase of the clock connects the
negative terminal of C2 to GND, and transfers
this positive generated voltage across C to C ,
2
4
the VDD storage capacitor. This voltage is
regulated to +5.5V. At this voltage, the internal
oscillator is disabled. Simultaneous with the
transfer of the voltage to C4, the positive side of
capacitor C is switched to V and the negative
1
CC
side is connected to GND, allowing the charge
pump cycle to repeat. The charge pump cycle
will continue as long as the operational
conditions for the internal oscillator are present.
Since both V+ and V– are separately generated
from VCC; in a no–load condition V+ and V– will
be symmetrical. Older charge pump approaches
that generate V– from V+ will show a decrease in
the magnitude of V– compared to V+ due to the
inherent inefficiencies in the design.
The charge pump clock rate typically operates
at 250kHz. The external capacitors can be as low
as 0.1µF with a 16V breakdown voltage rating.
VCC = +5V
ESD Tolerance
The SP3222H/3232H series incorporates
ruggedized ESD cells on all driver output
and receiver input pins.
The Human Body Model has been the generally
accepted ESD testing method for semiconduc-
tors. This method is also specified in MIL-STD-
883, Method 3015.7 for ESD testing. The premise
of this ESD test is to simulate the human body’s
potential to store electro-static energy and
discharge it to an integrated circuit. The
simulation is performed by using a test model as
shown in Figure 17. This method will test the
IC’s capability to withstand an ESD transient
during normal handling such as in manufacturing
areas where the ICs tend to be handled
frequently.
For the Human Body Model, the current
limiting resistor (RS) and the source capacitor
(CS) are 1.5kΩ and 100pF, respectively.
+
C1 –
–5V
+5V
+
C2 –
–5V
Figure 12. Charge Pump — Phase 1
VCC = +5V
C4
+ – VDD Storage Capacitor
– + VSS Storage Capacitor
C3
+
C1 –
Figure 13. Charge Pump — Phase 2
+
C2 –
–10V
C4
+ – VDD Storage Capacitor
– + VSS Storage Capacitor
C3
Rev. 6/27/03
SP3222H/3232H 3.3V, 460 Kbps RS-232 Transceivers
11
© Copyright 2003 Sipex Corporation
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