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FAN5067

ACPI Dual Switch Controller

Fairchild Semiconductor 

FAN5067

PRODUCT SPECIFICATION

300

200

ESR (mΩ)

100

47 100

200

C (µF)

300 330 400

Figure 6. Recommended C vs. ESR for

Stable Operation of the Dual Output

Adjustable Dual Output

The adjustable dual output is intended to provide power to

SDRAM or DDR memory.

The output voltage of the Adjustable Dual is set with two

resistors as shown in Figure 4, according to the equation.

Vadj = 1.25V • -R----1----+----R-----2

R2

Dynamic Change of Adjust Output

There may be circumstances under which it is desired to

dynamically change the output of the adjustable dual output.

For example, a circuit that switches from 2.5V to 3.3V is

shown in Figure 7.

VADJ

VADJFB

Adjustable dual is generated by one external NPN bipolar

acting as a linear regulator from +5V main, and one linear

regulator internal to the FAN5067 from +5V standby, as

shown in Figure 4, and in the block diagram on the front

page. When main power is present, the NPN Q3 linear regu-

lates, and when main power is absent, the internal linear reg-

ulator is on. Q3 cannot be substituted with a MOSFET. If

used in one direction, the MOSFET’s body diode would per-

mit back-feed; if used in the other direction, it would short-

circuit the linear regulator action.

The state of the external MOSFET and the internal linear

regulator is controlled by the SLP_S3 and PWROK lines,

and additionally the SLP_S5 line, as shown in Figure 3.

When SLP_S5 is de-asserted, both the external MOSFET

and the internal linear regulator are off, and there is no out-

put voltage on the 3.3V SDRAM line.

3.3V

Figure 7. Circuit for Dynamic Change of Output Voltage

of the Adjustable

A potential problem arises when using this circuit, however:

When the transistor is turned on, the voltage on the VADJFB

pin abruptly drops, until the output of the linear regulator can

charge up the output caps. If the voltage to which it drops is

less than about 80% of 1.25V, or 1.00V, the OC limit will trip

and shut down the IC. This happens in this example because

(R2 || R3)

2.5V

•

-----------------------------------------

[(R2 || R3) + R1]

=

0.94V

If the SLP_S5 line is asserted, the adjustable dual output is

on. In this condition, if either the SLP_S3 or the PWROK

line, or both, are de-asserted, the linear regulator is on and

the MOSFET is off. Only in the case if both the SLP_S3 and

the PWROK lines are asserted, the MOSFET is on and the

linear regulator is off.

In a typical system, it is anticipated that standby current will

be a maximum of 365mA, and full-power current may be as

high as 2A. This places some significant constraints on the

selection of Q3. Since its input may be as low as (5V – 5%)

= 4.75V, there is only 4.75V – 3.3V = 1.45mV of VCE head-

room for its operation as a linear regulator. For this reason

the FAN5067 can provide up to 200mA of steady-state base

current. The TIP41A device shown has a sufficiently low

VCE, sat to guarantee worst-case regulation even at 2A IE with

this base current.

To avoide this problem, systems that intended to dynami-

cally change the output voltage of the adjustable dual output

should disable the OC protection with the circuit shown in

Figure 8.

+5V_SB

+

1µF

2N3906

1N4148

SS

CSS

500K

Figure 8. Circuit to Disable OC Protection

10

REV. 1.0.1 5/2/02

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