UT62L12816BSL-100LL Просмотр технического описания (PDF) - Utron Technology Inc

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UT62L12816BSL-100LL

128K X 16 BIT LOW POWER CMOS SRAM

Utron Technology Inc 



Rev. 1.4

UTRON

TIMING WAVEFORMS

READ CYCLE 1 (Address Controlled) (1,2)

Address

tAA

Dout

tOH

Previous data valid

UT62L12816

128K X 16 BIT LOW POWER CMOS SRAM

tRC

tOH

Data Valid

READ CYCLE 2 ( CE and OE Controlled) (1,3,4,5)

Address

CE

LB , UB

tRC

tAA

tACE

tBA

OE

Dout

tBLZ

High-Z

tOE

tCLZ

tOLZ

tBHZ

tCHZ

tOHZ

tOH

Data Valid

High-Z

Notes :

1. WE is high for read cycle.

2.Device is continuously selected OE =low, CE =low, LB or UB =low.

3.Address must be valid prior to or coincident with CE =low, LB or UB =low transition; otherwise tAA is the limiting parameter.

4.tCLZ, tBLZ, tOLZ, tCHZ, tBHZ and tOHZ are specified with CL=5pF. Transition is measured±500mV from steady state.

5.At any given temperature and voltage condition, tCHZ is less than tCLZ, tBHZ is less than tBLZ, tOHZ is less than tOLZ.

UTRON TECHNOLOGY INC.

1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.

TEL: 886-3-5777882 FAX: 886-3-5777919

6

P80050

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