SM5166 Просмотр технического описания (PDF) - Nippon Precision Circuits

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SM5166

PLL Synthesizer IC

Nippon Precision Circuits  

SM5166AV

MSB

LSB

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17

Input

Data

210 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 2 4 2 3 2 2 2 1 2 0

00100111010001000

Main counter

Swallow counter

(11-bit : 32 to 2047)

(5-bit : 0 to 31)

Latch selection bit : Set to "0"

Figure 3. Swallow counter and main counter frequency divider data example

Reference counter frequency divider setting

MSB

LSB

DATA 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17

212 211 210 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0

(Reference counter 13-bit : 5 to 8191)

LD output setting bit∗

Test bits : (15, 16) = (0, 0) for normal operation

Latch selection bit : Set to "1"

∗ : Normal operation when 1,

LOW-level output when 0.

Figure 4. Reference counter data and LD output setting format

Input data example

If the VCO output (fVCO) is trebled, the crystal

frequency is 12.8 MHz and the channel bandwidth

(fCH: comparator frequency (fR) × 3) is 25 kHz, then

the reference frequency divider ratio R is given by:

NR

=

X-----t--a---l

fCH

=

-f--XR----t-×-a---l-3-

=

0---.--01---22---5.--8--⁄---3-

=

1536

=

8 × 192

Therefore, the reference counter count is 192

(00011000000)2. The input data format is shown in

figure 5.

NIPPON PRECISION CIRCUITS—7

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