SL74HC573 Просмотр технического описания (PDF) - System Logic Semiconductor
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SL74HC573
System Logic Semiconductor
SL74HC573 Datasheet PDF : 5 Pages
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SL74HC573
AC ELECTRICAL CHARACTERISTICS(CL=50pF,Input tr=tf=6.0 ns)
Symbol
Parameter
tPLH, tPHL Maximum Propagation Delay, Input D to Q
(Figures 1 and 5)
tPLH, tPHL Maximum Propagation Delay,Latch Enable
to Q (Figures 2 and 5)
tPLZ, tPHZ Maximum Propagation Delay, Output Enable to Q
(Figures 3 and 6)
tPZH, tPZL Maximum Propagation Delay, Output Enable to Q
(Figures 3 and 6)
tTLH, tTHL Maximum Output Transition Time, Any Output
(Figures 1 and 5)
CIN
Maximum Input Capacitance
COUT Maximum Three-State Output Capacitance
(Output in High-Impedance State)
VCC
Guaranteed Limit
V 25 °C to ≤85°C ≤125°C Unit
-55°C
2.0 150
190
225
ns
4.5 30
38
45
6.0 26
33
38
2.0 160
200
240
ns
4.5 32
40
48
6.0 27
34
41
2.0 150
190
225
ns
4.5 30
38
45
6.0 26
33
38
2.0 150
190
225
ns
4.5 30
38
45
6.0 26
33
38
2.0 60
75
90
ns
4.5 12
15
18
6.0 10
13
15
-
10
10
10
pF
-
15
15
15
pF
Power Dissipation Capacitance (Per Enabled
Output)
CPD Used to determine the no-load dynamic power
consumption: PD=CPDVCC2f+ICCVCC
Typical @25°C,VCC=5.0 V
23
TIMING REQUIREMENTS (CL=50pF,Input tr=tf=6.0 ns)
VCC
Symbol
Parameter
V
tSU
Minimum Setup Time, Input D 2.0
to Latch Enable
4.5
(Figure 4)
6.0
th
Minimum Hold Time, Latch
2.0
Enable to Input D
4.5
(Figure 4)
6.0
tw
Minimum Pulse Width, Latch
2.0
Enable (Figure 2)
4.5
6.0
tr, tf Maximum Input Rise and Fall
2.0
Times (Figure 1)
4.5
6.0
25 °C to
-55°C
50
10
9
5
5
5
75
15
13
1000
500
400
Guaranteed Limit
≤85°C
65
13
11
5
5
5
95
19
16
1000
500
400
≤125°C
75
15
13
5
5
5
110
22
19
1000
500
400
pF
Unit
ns
ns
ns
ns
SLS
System Logic
Semiconductor
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