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SL74HC125N

Quad 3-State Noninverting Buffers

System Logic Semiconductor 

SL74HC125

AC ELECTRICAL CHARACTERISTICS(CL=50pF,Input tr=tf=6.0 ns)

Symbol

Parameter

tPLH, tPHL Maximum Propagation Delay, Input A to

Output Y (Figures 1 and 3)

tPLZ, tPHZ Maximum Propagation Delay, Output Enable toY

(Figures 2 and 4)

tPZL, tPZH Maximum Propagation Delay, Output Enable toY

(Figures 2 and 4)

tTLH, tTHL Maximum Output Transition Time, Any Output

(Figures 1 and 3)

CIN

Maximum Input Capacitance

COUT Maximum Three-State Output Capacitance

(Output in High-Impedance State)

VCC

Guaranteed Limit

V 25 °C to ≤85°C ≤125°C Unit

-55°C

2.0 90

115

135

ns

4.5 18

23

27

6.0 15

20

23

2.0 120

150

180

ns

4.5 24

30

36

6.0 20

26

31

2.0 90

115

135

ns

4.5 18

23

27

6.0 15

20

23

2.0 60

75

90

ns

4.5 12

15

18

6.0 10

13

15

-

10

10

10

pF

-

15

15

15

pF

Power Dissipation Capacitance (Per Buffer)

CPD Used to determine the no-load dynamic power

consumption:

PD=CPDVCC2f+ICCVCC

Typical @25°C,VCC=5.0 V

45

pF

Figure 1. Switching Waveforms

Figure 2. Switching Waveforms

SLS

System Logic

Semiconductor

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