SL11R Просмотр технического описания (PDF) - Cypress Semiconductor
Номер в каталоге
Компоненты Описание
Список матч
SL11R Datasheet PDF : 85 Pages
| |||
SL11R
3.6 Clock Generator
A 12, 48 MHz external Crystal, or logic-level clock can be used with the SL11R. Two pins, X1 and X2, are provided to connect a
low cost crystal circuit to the device. If a logic-level clock is available, it may be connected directly to the X1 pin instead of a crystal.
Register C006 must be configured appropriately depending on the frequency used.
3.7 USB Interface
The SL11R has a built-in SIE and USB transceiver that meet the USB (Universal Serial Bus) specification v1.1. The transceiver
is capable of transmitting or receiving serial data at the USB maximum data rate of 12 Mbits/sec. The SL11R Controller supports
four endpoints. Endpoint 0 is the default pipe and is used to initialize and manipulate the peripheral device. It also provides access
to the peripheral device’s configuration information, and supports control transfers. Endpoint 1,2, and 3 support Interrupt transfers,
Bulk transfers (up to 64 Bytes/packet), or Isochronous transfers (up to 1024 Bytes/packet size).
3.8 Processor Control Registers
The SL11R provides software control registers that can be used to configure the chip mode, the clock generator, the software
breakpoint, and to read the BIOS version.
3.9 Interrupts
The SL11R provides 127 interrupt vectors for it’s BIOS software interface (see [Ref. 1] SL11R_BIOS).
3.10 UART Interface
The SL11R has a built-in UART interface, which supports data rates from 900 baud to 115.2K Baud. It can be used as a
development port or for other interface requirements. The Cypress development environment for the SL11R chip includes a
debugger and assembler. Optional “C” compiler is also available[1]. You can download modified code to internal SRAM and debug
it using the built-in Breakpoint register and Breakpoint Interrupt to break on any specified address location.
3.11 *2-wire Serial EEPROM Interface
The SL11R provides an interface to an external serial EEPROM. The interface is implemented using General Purpose I/O signals.
A variety of serial EEPROM formats can be supported; currently the BIOS ROM supports a two-wire serial EEPROM. A serial
EEPROM can be used to store specific Peripheral USB configuration and value-added functions. In addition, serial EEPROM can
be used for field product upgrades.
3.12 External SRAM/DRAM/EPROM Interface
The SL11R provides a multiplexed address port and an 8/16-bit data port. This port can be configured to interface to an external
SRAM, EPROM or DRAM. The port provides nRAS; nCASL, nCASH, nDRAMWR and nDRAMOE control signals for data access
and refresh cycles to the DRAM.
3.13 General Timers and Watch Dog Timer
The SL11R has two built in programmable timers that can provide an interrupt to the SL11R Engine. On every clock tick which is
1 microsecond the timers decrement. An interrupt occurs when the timer reaches zero. A separate Watchdog timer is also
provided to provide a fail-safe mechanism. The Watchdog timer can also interrupt the SL11R processor.
3.14 Special GPIO Functionality for Suspend, Resume and Low Power modes
The SL11R CPU supports suspend, resume and CPU low power modes. The SL11R BIOS assigns GPIO29 for the USB DATA+
line pull-up (this pin can simulate USB cable removal or insertion while the USB power is still applied to the board) and the GPIO20
for controlling the power off function.
3.15 Programmable Pulse/PWM Interface
The SL11R has four built-in PWM output channels available under 8/16-bit DMA mode. Each channel provides a programmable
timing generator sequence that can be used to interface to various lines CCD, CIS, CMOS image sensors or can be used for
other various applications. This feature is only available in the 8/16-bit DMA Mode.
Note:
1. Contact Cypress for details. (support@scanlogic.com)
Document #: 38-08006 Rev. **
Page 11 of 85
Share Link: 