CS8405A-CZ Просмотр технического описания (PDF) - Cirrus Logic
Номер в каталоге
Компоненты Описание
Список матч
CS8405A-CZ Datasheet PDF : 37 Pages
| |||
CS8405A
SWITCHING CHARACTERISTICS
(Inputs: Logic 0 = 0 V, Logic 1 = VL+; CL = 20 pF)
Parameter
RST pin Low Pulse Width
OMCK Frequency for OMCK = 512 * Fso
OMCK Low and High Width for OMCK = 512 * Fso
OMCK Frequency for OMCK = 384 * Fso
OMCK Low and High Width for OMCK = 384 * Fso
OMCK Frequency for OMCK = 256 * Fso
OMCK Low and High Width for OMCK = 256 * Fso
Frame Rate
AES3 Transmitter Output Jitter
Symbol Min
200
4.1
7.2
3.1
10.8
2.0
14.4
8.0
-
Typ Max Units
-
-
µs
-
55.3 MHz
-
-
ns
-
41.5 MHz
-
-
ns
-
27.7 MHz
-
-
ns
-
108.0 kHz
-
1
ns
SWITCHING CHARACTERISTICS - SERIAL AUDIO PORTS
(Inputs: Logic 0 = 0 V, Logic 1 = VL+; CL = 20 pF)
Parameter
Symbol Min Typ Max Units
SDIN Setup Time Before ISCLK Active Edge
(Note 6)
tds
20
-
-
ns
SDIN Hold Time After ISCLK Active Edge
(Note 6)
tdh
20
-
-
ns
Master Mode
OMCK to ISCLK active edge delay
OMCK to ILRCK delay
ISCLK and ILRCK Duty Cycle
(Note 6) tsmd
(Note 7) tlmd
0
-
10
ns
0
-
10
ns
-
50
-
%
Slave Mode
ISCLK Period
(Note 8) tsckw
36
-
-
ns
ISCLK Input Low Width
tsckl
14
-
-
ns
ISCLK Input High Width
tsckh
14
-
-
ns
ISCLK Active Edge to ILRCK Edge
(Note 6,7,9) tlrckd
20
-
-
ns
ILRCK Edge Setup Before ISCLK Active Edge (Note 6,7,10) tlrcks
20
-
-
ns
Notes: 6. The active edge of ISCLK is programmable.
7. The polarity of ILRCK is programmable.
8. No more than 128 SCLK per frame.
9. Prevents the previous ISCLK edge from being interpreted as the first one after ILRCK has changed.
10. This setup time ensures that this ISCLK edge is interpreted as the first one after ILRCK has changed
6
DS469F2
Share Link: 