CS8405A-CS Просмотр технического описания (PDF) - Cirrus Logic

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CS8405A-CS

96 kHz Digital Audio Interface Transmitter

Cirrus Logic 

CS8405A

8. CONTROL PORT REGISTER BIT DEFINITIONS

8.1 Control 1 (01h)

7

6

5

4

3

2

1

0

0

VSET

0

MUTEAES

0

INT1

INT0

TCBLD

VSET - Transmitted Validity bit level

Default = ‘0’

0 - Indicates data is valid, linear PCM audio data

1 - Indicates data is invalid or not linear PCM audio data

MUTEAES - Mute control for the AES transmitter output

Default = ‘0’

0 - Not Muted

1 - Muted

INT1:0 - Interrupt output pin (INT) control

Default = ‘00’

00 - Active high; high output indicates interrupt condition has occurred

01 - Active low, low output indicates an interrupt condition has occurred

10 - Open drain, active low. Requires an external pull-up resistor on the INT pin.

11 - Reserved

TCBLD - Transmit Channel Status Block pin (TCBL) direction specifier

Default = ‘0’

0 - TCBL is an input

1 - TCBL is an output

8.2 Control 2 (02h)

7

6

5

4

3

2

1

0

0

0

0

0

0

MMT

MMTCS

MMTLR

MMT - Select AES3 transmitter mono or stereo operation

Default = ‘0’

0 - Normal stereo operation

1 - Output either left or right channel inputs into consecutive subframe outputs (mono

mode, left or right is determined by MMTLR bit)

MMTCS - Select A or B channel status data to transmit in mono mode

Default = ‘0’

0 - Use channel A CS data for the A subframe and use channel B CS data for the B subframe

1 - Use the same CS data for both the A and B subframe outputs. If MMTLR = 0, use the

left channel CS data. If MMTLR = 1, use the right channel CS data.

18

DS469F2

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