CS8405A-IS(2002) Просмотр технического описания (PDF) - Cirrus Logic

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CS8405A-IS
(Rev.:2002)

96 kHz Digital Audio Interface Transmitter

Cirrus Logic 

CS8405A

MAP byte. The MAP auto increment bit (INCR)

may be set or not, as desired. To begin a read, bring

CS low, send out the chip address and set the

read/write bit (R/W) high. The next falling edge of

CCLK will clock out the MSB of the addressed

register (CDOUT will leave the high impedance

state). If the MAP auto increment bit is set to 1, the

data for successive registers will appear consecu-

tively.

6.2 Two-Wire Mode

In Two-Wire Mode, SDA is a bidirectional data

line. Data is clocked into and out of the part by the

clock, SCL, with the clock to data relationship as

shown in Figure 9. There is no CS pin. Each indi-

vidual CS8405A is given a unique address. Pins

AD0, AD1, and AD2 form the three least signifi-

cant bits of the chip address, and should be con-

nected to VL+ or DGND as desired. The upper four

bits of the seven-bit address field are fixed at 0010.

To communicate with a CS8405A, the chip address

field, which is the first byte sent to the CS8405A,

should match 0010 followed by the settings of

AD2, AD1, and AD0. The eighth bit of the address

is the R/W bit. If the operation is a write, the next

byte is the Memory Address Pointer (MAP) which

selects the register to be read or written. If the op-

eration is a read, the contents of the register pointed

to by the MAP will be output. Setting the auto in-

crement bit in MAP allows successive reads or

writes of consecutive registers. Each byte is sepa-

rated by an acknowledge bit, ACK, which is output

from the CS8405A after each input byte is read.

The ACK bit is input to the CS8405A from the mi-

crocontroller after each transmitted byte. The Two-

Wire Mode is compatible with the I2C protocol.

6.3 Interrupts

The CS8405A has a comprehensive interrupt capa-

bility. The INT output pin is intended to drive the

interrupt input pin on the host microcontroller. The

INT pin may be set to be active low, active high or

active low with no active pull-up transistor. This

last mode is used for active low, wired-OR hook-

ups, with multiple peripherals connected to the mi-

crocontroller interrupt input pin.

Many conditions can cause an interrupt, as listed in

the interrupt status register descriptions. Each

source may be masked off by a bit in the mask reg-

isters. In addition, each source may be set to rising

edge, falling edge, or level sensitive. Combined

with the option of level sensitive or edge sensitive

modes within the microcontroller, many different

set-ups are possible, depending on the needs of the

equipment designer.

SDA

0010

N ote 1

Note 2

Note 3

A D 2 -0 R /W A C K D ATA 7-0 A C K D ATA 7-0 A C K

SCL

S ta rt

S to p

N o te 1: A D 2 is derived from a resistor a ttached to the E M PH pin ,

A D 1 a nd A D 0 a re determ ined by the state of the corresp onding pins

N o te 2 : If o p e ra tio n is a w rite , this b yte c o n ta in s th e M e m o ry A d d re ss P o in te r, M A P

N o te 3: If o peration is a read, the la st bit of the re ad sh ould be a N A C K (high )

Figure 9. Control Port Timing in Two-Wire Mode

DS469PP4

15

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