CS8415A-IZ Просмотр технического описания (PDF) - Cirrus Logic
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CS8415A-IZ Datasheet PDF : 42 Pages
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CS8415A
SWITCHING CHARACTERISTICS - SERIAL AUDIO PORTS
(Inputs: Logic 0 = 0 V, Logic 1 = VL+; CL = 20 pF)
Parameter
Symbol Min Typ Max Units
OSCLK Active Edge to SDOUT Output Valid
(Note 7) tdpd
-
-
20
ns
Master Mode
RMCK to OSCLK active edge delay
RMCK to OLRCK delay
OSCLK and OLRCK Duty Cycle
(Note 7) tsmd
(Note 8) tlmd
0
-
10
ns
0
-
10
ns
-
50
-
%
Slave Mode
OSCLK Period
(Note 9) tsckw
36
-
-
ns
OSCLK Input Low Width
tsckl
14
-
-
ns
OSCLK Input High Width
tsckh
14
-
-
ns
OSCLK Active Edge to OLRCK Edge
(Note 7,8,10) tlrckd
20
-
-
ns
OLRCK Edge Setup Before OSCLK Active Edge
(Note tlrcks
20
-
-
ns
7,8,11)
Notes: 7. The active edges of OSCLK are programmable.
8. The polarity OLRCK is programmable.
9. No more than 128 SCLK per frame.
10. This delay is to prevent the previous OSCLK edge from being interpreted as the first one after OLRCK
has changed.
11. This setup time ensures that this OSCLK edge is interpreted as the first one after OLRCK has changed.
OSCLK
(output)
OLRCK
(output)
t smd
RMCK
(output)
RMCK
(output)
Hardware M ode
Software M ode
t lm d
Figure 1. Audio Port Master Mode Timing
OLRCK
(input)
OSCLK
(input)
t lrckd
t lrcks
SDOUT
t sckh
tsckl
t sckw
tdpd
Figure 2. Audio Port Slave Mode and Data Input Timing
7
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