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CS8415A-IZ

96 kHz Digital Audio Interface Receiver

Cirrus Logic 

CS8415A

SCL, with the clock to data relationship as shown

in Figure 9. There is no CS pin. Each individual

CS8415A is given a unique address. Pins AD0 and

AD1 form the two least significant bits of the chip

address and should be connected to VL+ or DGND

as desired. The EMPH pin is used to set the AD2

bit by connecting a resistor from the EMPH pin to

VL+ or to DGND. The state of the pin is sensed

while the CS8415A is being reset. The upper 4 bits

of the 7-bit address field are fixed at 0010. To com-

municate with a CS8415A, the chip address field,

which is the first byte sent to the CS8415A, should

match 0010 followed by the settings of the EMPH,

AD1, and AD0. The eighth bit of the address is the

R/W bit. If the operation is a write, the next byte is

the Memory Address Pointer (MAP) which selects

the register to be read or written. If the operation is

a read, the contents of the register pointed to by

the MAP will be output. Setting the auto increment

bit in MAP allows successive reads or writes of

consecutive registers. Each byte is separated by

an acknowledge bit. The ACK bit is output from the

CS8415A after each input byte is read, and is input

to the CS8415A from the microcontroller after each

transmitted byte. I2C mode is supported only with

VL+ in 5V mode.

6.3 Interrupts

The CS8415A has a comprehensive interrupt ca-

pability. The INT output pin is intended to drive the

interrupt input pin on the host microcontroller. The

INT pin may be set to be active low, active high or

active low with no active pull-up transistor. This last

mode is used for active low, wired-OR hook-ups,

with multiple peripherals connected to the micro-

controller interrupt input pin.

Many conditions can cause an interrupt, as listed in

the interrupt status register descriptions. Each

source may be masked off through mask register

bits. In addition, each source may be set to rising

edge, falling edge, or level sensitive. Combined

with the option of level sensitive or edge sensitive

modes within the microcontroller, many different

configurations are possible, depending on the

needs of the equipment designer.

SDA

Note 1

Note 2

Note 3

0010 AD2-0 R/W ACK DATA7-0 ACK DATA7-0 ACK

SCL

Start

Figure 9. Control Port Timing in I2C Mode

Stop

Notes: 1. AD2 is derived from a resistor attached to the EMPH pin.

AD1 and AD0 are determined by the state of the corresponding pins.

2. If operation is a write, this byte contains the Memory Address Pointer, MAP.

3. If operation is a read, the last bit of the read should be NACK (high).

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