Si3050 + Si3018/19
Table 7. Switching Characteristics—Serial Peripheral Interface
(VIO = 3.0 to 3.6 V, TA = 0 to 70 °C for K-Grade, CL = 20 pF)
Parameter*
Cycle Time SCLK
Rise Time, SCLK
Fall Time, SCLK
Delay Time, SCLK Fall to SDO Active
Delay Time, SCLK Fall to SDO
Transition
Delay Time, CS Rise to SDO Tri-state
Setup Time, CS to SCLK Fall
Hold Time, SCLK to CS Rise
Setup Time, SDI to SCLK Rise
Hold Time, SCLK Rise to SDI Transition
Delay time between chip selects
Propagation Delay, SDI to SDITHRU
Symbol
Test
Conditions
Min
Typ
tc
61.03
—
tr
—
—
tf
—
—
td1
—
—
td2
—
—
td3
—
—
tsu1
25
—
th1
20
—
tsu2
25
—
th2
20
—
tcs
220
—
—
6
Max
—
25
25
20
20
20
—
—
—
—
—
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
*Note: All timing (except Rise and Fall time) is referenced to the 50% level of the waveform. Input test levels are
VIH = VD – 0.4 V, VIL = 0.4 V. Rise and Fall times are referenced to the 20% and 80% levels of the waveform.
SCLK
CS
SDI
SDO
tr
tsu1
td1
tc
tsu2
th2
td2
tf
th1
tcs
td3
Figure 3. SPI Timing Diagram
Rev. 1.31
11