HD64F7052F40 Просмотр технического описания (PDF) - Renesas Electronics

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HD64F7052F40

RISC Engine Manual

Renesas Electronics 

14.1.3 Pin Configuration ................................................................................................. 441

14.1.4 Register Configuration ......................................................................................... 442

14.2 Register Descriptions......................................................................................................... 443

14.2.1 Receive Shift Register (RSR)............................................................................... 443

14.2.2 Receive Data Register (RDR) .............................................................................. 444

14.2.3 Transmit Shift Register (TSR).............................................................................. 444

14.2.4 Transmit Data Register (TDR) ............................................................................. 445

14.2.5 Serial Mode Register (SMR)................................................................................ 445

14.2.6 Serial Control Register (SCR).............................................................................. 448

14.2.7 Serial Status Register (SSR)................................................................................. 452

14.2.8 Bit Rate Register (BRR)....................................................................................... 456

14.2.9 Serial Direction Control Register (SDCR) ........................................................... 463

14.2.10 Inversion of SCK Pin Signal ................................................................................ 464

14.3 Operation ........................................................................................................................... 464

14.3.1 Overview .............................................................................................................. 464

14.3.2 Operation in Asynchronous Mode........................................................................ 466

14.3.3 Multiprocessor Communication ........................................................................... 476

14.3.4 Synchronous Operation ........................................................................................ 484

14.4 SCI Interrupt Sources and the DMAC............................................................................... 495

14.5 Usage Notes ....................................................................................................................... 496

14.5.1 TDR Write and TDRE Flag.................................................................................. 496

14.5.2 Simultaneous Multiple Receive Errors ................................................................ 496

14.5.3 Break Detection and Processing (Asynchronous Mode Only)............................. 497

14.5.4 Sending a Break Signal (Asynchronous Mode Only) .......................................... 497

14.5.5 Receive Error Flags and Transmitter Operation (Synchronous Mode Only)....... 497

14.5.6 Receive Data Sampling Timing and Receive Margin in Asynchronous Mode.... 497

14.5.7 Constraints on DMAC Use .................................................................................. 499

14.5.8 Cautions on Synchronous External Clock Mode.................................................. 499

14.5.9 Caution on Synchronous Internal Clock Mode .................................................... 499

Section 15 Hitachi Controller Area Network (HCAN) ............................................ 501

15.1 Overview............................................................................................................................ 501

15.1.1 Features ................................................................................................................ 501

15.1.2 Block Diagram...................................................................................................... 502

15.1.3 Pin Configuration ................................................................................................. 503

15.1.4 Register Configuration ......................................................................................... 504

15.2 Register Descriptions......................................................................................................... 506

15.2.1 Master Control Register (MCR)........................................................................... 506

15.2.2 General Status Register (GSR)............................................................................. 507

15.2.3 Bit Configuration Register (BCR)........................................................................ 508

15.2.4 Mailbox Configuration Register (MBCR)............................................................ 512

15.2.5 Transmit Wait Register (TXPR) .......................................................................... 512

15.2.6 Transmit Wait Cancel Register (TXCR) .............................................................. 513

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