XC164D(2005) Просмотр технического описания (PDF) - Infineon Technologies

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XC164D
(Rev.:2005)

16-Bit Single-Chip Microcontroller with C166SV2 Core

Infineon Technologies 

XC164D

Derivatives

Summary of Features

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Summary of Features

• High Performance 16-bit CPU with 5-Stage Pipeline

– 25 ns Instruction Cycle Time at 40 MHz CPU Clock (Single-Cycle Execution)

– 1-Cycle Multiplication (16 × 16 bit), Background Division (32 / 16 bit) in 21 Cycles

– 1-Cycle Multiply-and-Accumulate (MAC) Instructions

– Enhanced Boolean Bit Manipulation Facilities

– Zero-Cycle Jump Execution

– Additional Instructions to Support HLL and Operating Systems

– Register-Based Design with Multiple Variable Register Banks

– Fast Context Switching Support with Two Additional Local Register Banks

– 16 Mbytes Total Linear Address Space for Code and Data

– 1024 Bytes On-Chip Special Function Register Area (C166 Family Compatible)

• 16-Priority-Level Interrupt System with up to 75 Sources, Sample-Rate down to 50 ns

• 8-Channel Interrupt-Driven Single-Cycle Data Transfer Facilities via

Peripheral Event Controller (PEC), 24-Bit Pointers Cover Total Address Space

• Clock Generation via on-chip PLL (factors 1:0.15 … 1:10), or

via Prescaler (factors 1:1 … 60:1)

• On-Chip Memory Modules

– 2 Kbytes On-Chip Dual-Port RAM (DPRAM)

– 2 Kbytes On-Chip Data SRAM (DSRAM)

– 2 Kbytes On-Chip Program/Data SRAM (PSRAM)

– up to 128 Kbytes On-Chip Program Memory (Flash Memory)

• On-Chip Peripheral Modules

– Two 16-Channel General Purpose Capture/Compare Units (12 Input/Output Pins)

– Capture/Compare Unit for flexible PWM Signal Generation (CAPCOM6)

(3/6 Capture/Compare Channels and 1 Compare Channel)

– Multi-Functional General Purpose Timer Unit with 5 Timers

– Two Synchronous/Asynchronous Serial Channels (USARTs)

– Two High-Speed-Synchronous Serial Channels

– On-Chip TwinCAN Interface (Rev. 2.0B active) with 32 Message Objects

(Full CAN/Basic CAN) on Two CAN Nodes, and Gateway Functionality

– On-Chip Real Time Clock

• Idle, Sleep, and Power Down Modes with Flexible Power Management

• Programmable Watchdog Timer and Oscillator Watchdog

• Up to 12 Mbytes External Address Space for Code and Data

– Programmable External Bus Characteristics for Different Address Ranges

– Multiplexed or Demultiplexed External Address/Data Buses

– Selectable Address Bus Width

– 16-Bit or 8-Bit Data Bus Width

– Four Programmable Chip-Select Signals

• Up to 79 General Purpose I/O Lines,

partly with Selectable Input Thresholds and Hysteresis

Data Sheet

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V1.0, 2005-01

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