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SAA7104E Datasheet PDF : 78 Pages
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Philips Semiconductors
SAA7104E; SAA7105E
Digital video encoder
Table 4: Pin description…continued
Symbol
Pin
Type [1] Description
GREEN_VBS_CVBS C7
O
analog output of GREEN or VBS or CVBS signal
RED_CR_C_CVBS C8
TDO
D1
O
analog output of RED or CR or C or CVBS signal
O
test data output for BST [3]
RESET
D2
I
reset input; active LOW
TMS
D3
I/pu test mode select input for BST [3]
VDDD2
VDDD3
VDDD4
VDDA3
VSM
D4
S
digital supply voltage 2 (3.3 V for I/Os)
D4
S
digital supply voltage 3 (3.3 V for core)
D4
S
digital supply voltage 4 (3.3 V for core)
D6
S
analog supply voltage 3 (3.3 V for oscillator)
D7
O
vertical synchronization output to monitor
(non-interlaced auxiliary RGB)
HSM_CSYNC
D8
O
horizontal synchronization output to monitor
(non-interlaced auxiliary RGB) or composite sync for
RGB-SCART
TCK
E1
I/pu
test clock input for BST [3]
SCL
E2
I(/O) serial clock input (I2C-bus) with inactive output path
HSVGC
E3
I/O
horizontal synchronization output to VGC (optional
input) [6]
reserved
E12
-
to be reserved for future applications
VSVGC
F1
I/O
vertical synchronization output to VGC (optional
input) [6]
PIXCLKI
F2
I
pixel clock input (looped through)
PD3
VDDD1
F3
I
pixel data 3 [2]; MSB − 4 with CB-Y-CR 4 : 2 : 2
F4
S
digital supply voltage 1 for pins PD11 to PD0,
PIXCLKI, PIXCLKO, FSVGC, VSVGC, HSVGC, CBO
and TVD
TVD
F12
O
interrupt if TV is detected at DAC output
FSVGC
G1
I/O
frame synchronization output to Video Graphics
Controller (VGC) (optional input) [6]
SDA
G2
I/O
serial data input/output (I2C-bus)
CBO
G3
I/O
composite blanking output to VGC; active LOW [6]
PIXCLKO
G4
O
pixel clock output to VGC
PD2
PD1
PD0
H1
I
pixel data 2 [2]; MSB − 5 with CB-Y-CR 4 : 2 : 2
H2
I
pixel data 1 [2]; MSB − 6 with CB-Y-CR 4 : 2 : 2
H3
I
pixel data 0 [2]; MSB − 7 with CB-Y-CR 4 : 2 : 2
[1] Pin type: I = input, O = output, S = supply, pu = pull-up.
[2] See Table 12 to Table 18 for pin assignment.
[3] In accordance with the ‘IEEE1149.1’ standard the pins TDI, TMS, TCK and TRST are input pins with an
internal pull-up resistor and TDO is a 3-state output pin.
[4] For board design without boundary scan implementation connect TRST to ground.
[5] This pin provides easy initialization of the BST circuit. TRST can be used to force the Test Access Port
(TAP) controller to the TEST_LOGIC_RESET state (normal operation) at once.
[6] Pins FSVGC, VSVGC, CBO, HSVGC and TTXRQ_XCLKO2 are used for bootstrapping; see Section 7.1.
SAA7104E_SAA7105E_2
Product data sheet
Rev. 02 — 23 December 2005
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
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