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SAA8122A

Digital Still Camera Processor (ImagIC family)

Philips Electronics 

Philips Semiconductors

SAA8122A

Digital Still Camera Processor (ImagIC family)

Table 3: Pin description…continued

Symbol

Pin

Type

SC_CLE

M18

O

SD_A[12]

N1

O

SD_A[13]

N2

O

SD_A[14]

N3

O

SD_A[10]

N4

O

SD_A[6]

N5

O

SD_A[5]

N6

O

VDD

VDD

VDD

VDD

VDD

SC_ALE

N7

-

N8

-

N9

-

N10

-

N11

-

N12

O

PC2_CE1

N13

O

PC2_CE2

N14

O

PC_REG

N15

O

PC_WAIT1

N16

O

IOWR_WE

N17

O

IORD_RE

N18

O

SD_CLKOUT P1

O

SD_CLKIN

P2

I

SD_CS2

P3

O

SD_CLKEN

P4

O

SD_A[11]

P5

O

VDD

P6

-

SD_D[7]

P7

I/O

IO25

P8

I/O

IO38

P9

I/O

A25

P10

I/O

A21

P11

I/O

VDD

P12

-

A14

P13

I/O

SCLK

P14

O

A9

P15

I/O

CAS0

P16

O

PC1_CE1

P17

O

PC1_CE2

P18

O

SD_CS0

R1

O

SD_CS1

R2

O

SD_CS3

R3

O

9397 750 07048

Objective specification

Description

EBIU controller CLE signal for SSFDC card

SDRAM controller address bus bit 12

SDRAM controller address bus bit 13

SDRAM controller address bus bit 14

SDRAM controller address bus bit 10

SDRAM controller address bus bit 6

SDRAM controller address bus bit 5

supply voltage

supply voltage

supply voltage

supply voltage

supply voltage

EBIU controller ALE signal for SSFDC card

EBIU controller CE1 signal for PC card 2; active LOW

EBIU controller CE2 signal for PC card 2; active LOW

EBIU controller REG signal for PC cards; active LOW

EBIU controller WAIT signal for PC card 1; active LOW

EBIU controller IORD signal for PC cards; active LOW

EBIU controller IORD signal for PC cards; active LOW

SDRAM controller clock output

SDRAM controller clock input

SDRAM controller chip select for memory 2; active LOW

SDRAM controller clock enable

SDRAM controller address bus bit 11

supply voltage

SDRAM controller data bus bit 7

I/O port 3 bit 1

I/O port 4 bit 6

EBIU A25 (Strapin[0] during boot sequence)

EBIU A21 (Strapin[4] during boot sequence)

supply voltage

EBIU A14

EBIU controller clock signal for external peripherals

EBIU A9

EBIU controller CAS signal for DRAM memory for lower byte; used as data

strobe signal for lower byte for general chip select; active LOW

EBIU controller CE1 signal for PC card 1; active LOW

EBIU controller CE2 signal for PC card 1; active LOW

SDRAM controller chip select for memory 0; active LOW

SDRAM controller chip select for memory 1; active LOW

SDRAM controller chip select for memory 3; active LOW

Rev. 01 — 20 April 2000

© Philips Electronics N.V. 2000. All rights reserved.

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