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SAA4952WP

Memory controller

Philips Electronics 

Philips Semiconductors

Memory controller

Objective specification

SAA4952WP

Table 3 Vertical acquisition related pulses

ADDRESS

(HEX)

50

51

52

REGISTER

FUNCTION

VWE1STA(1)

VWE1STO(1)

VAMSB

start of vertical write enable (lower 8 of 9 bits)

stop of vertical write enable (lower 8 of 9 bits)

bit 0: MSB of VWE1STA

bit 1: MSB of VWE1STO

bit 2:

BRE = 0: normal operation

BRE = 1: RE output is blanking every second line in program scan mode

bit 3:

BWE = 0: normal operation

BWE = 1: WE2 output is blanking every second line in program scan mode

bit 4: BPRR: Blanking Phase Relation RE for program

BPRR = 0: AND connection HRDFL and HRE

BPRR = 1: AND connection HRDFLN and HRE

bit 5: BPRW: Blanking Phase Relation WE2 for program

BPRW = 0: AND connection HRDFL and HWE2

BPRW = 1: AND connection HRDFLN and HWE2

bit 6: BVRA: Blanking Vertical Reset Acquisition

BVRA = 0: reset blanking disabled

BVRA = 1: reset blanking enabled

bit 7: BVRD: Blanking Vertical Reset Display

BVRD = 0: reset blanking disabled

BVRD = 1: reset blanking enabled

Note

1. VWE1 programmable in steps of 1 line (64 µs).

1997 Jun 10

10

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