SAA4960 Просмотр технического описания (PDF) - Philips Electronics
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SAA4960 Datasheet PDF : 24 Pages
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Philips Semiconductors
Integrated PAL comb filter
Preliminary specification
SAA4960
The input signals of the control and clock processing
(CLOCK CONTROL) are:
HDET: analog horizontal pulse from sync separator
VDET: analog vertical pulse from sync separator
FSC: subcarrier frequency (fsc or 2 × fsc)
FSCSW: reference frequency selection
BYP: BYPASS control signal
SSYN: vertical synchronous mode selection for BYP
and polarity selection of BYP.
The output signals are:
CL3: system clock (3 × fsc)
HSEL’s: line start signals for the delay lines
STOPS: forces the comb filter via the switches S2A,
S2B and S2C into the BYPASS-mode (always
asynchronous) or COMB-mode (synchronous or
asynchronous with VINT; depending on SSYN)
COMBENA: HIGH during COMB-mode; otherwise
LOW.
Table 10 Function of STOPS signal
STOPS-STATE
LOW
HIGH
SELECTED MODE
COMB
BYPASS
Table 11 Function of signal switch S1
LPFION-STATE
DELAY LINE INPUT
LOW
HIGH
Floating
non-pre-filtered input signal
Yext/CVBS
pre-filtered input signal Yext/CVBS
pre-filtered input signal Yext/CVBS
SIGNAL SWITCH S2A
For the CVBSO output two signals can be selected via the
signal switch S2A.
Table 12 CVBSO output signal
STOPS-STATE
CVBSO OUTPUT
SIGNAL
LOW
delayed input CVBSDL
HIGH
non-delayed input
Yext/CVBS
MODE
COMB
BYPASS
SIGNAL SWITCHES S2B AND S2C
Two switches are included to bypass the comb filter signal
processing. The input video signal Cext for the switch S2C
is internally biased.
For the YO output two signals can be selected via S2B.
HORIZONTAL AND VERTICAL SYNC SEPARATOR
A build-in sync separator circuit generates the HDET and
VDET signals from the Yext/CVBS input signal. This circuit
is still working properly at input signals with a 12 dB
attenuated sync in a normal 700 mV black-to-white video
signal (see Fig.4).
Table 13 YO output signal
STOPS-STATE
LOW
HIGH
YO OUTPUT SIGNAL
YCOMB
(combed luminance)
input Yext/CVBS
MODE
COMB
BYPASS
CLAMP
The black level clamping of the video input signal is
performed by the sync separator stage. The clamping level
is nearly adequate to the voltage at REFDL (pin 24).
SIGNAL SWITCH S1
The switch is included to bypass the low-pass input filter.
For the CVBS input of the delay line block two signals can
be selected via the slow signal switch S1.
For the CO output two signals can be selected via S2C.
Table 14 CO output signal
STOPS-STATE
LOW
HIGH
CO OUTPUT SIGNAL
CCOMB
(combed chrominance)
input Cext
MODE
COMB
BYPASS
1996 Oct 15
8
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