HD74CDC2509B Просмотр технического описания (PDF) - Hitachi -> Renesas Electronics

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HD74CDC2509B

3.3-V Phase-lock Loop Clock Driver

Hitachi -> Renesas Electronics 

HD74CDC2509B

Switching Characteristics (CL = 30 pF, Ta = 0 to 85°C)

Item

Phase error time

Symbol

t pe

VCC = 3.3 V±0.3 V

Min Typ Max

–150 —

150

Unit

ps

Between output pins skew *1 tsk (O)

—

—

200 ps

From (Input) To (Output)

66 MHz <

CLKIN↑

≤ 100 MHz

Any Y or

FBOUT

FBIN↑

Any Y or

FBOUT

Cycle to cycle jitter

–100 —

100 ps

F (clkin =

100 MHz)

Any Y or

FBOUT

Duty cycle

45

—

55

%

F (clkin =

Any Y or

66 to 100 MHz) FBOUT

Output rise / fall time

t TLH

5.0 —

1.0 volts/ns

Any Y or

FBOUT

t THL

5.0 —

1.0

Any Y or

FBOUT

Analog power supply

rejection

(DC to 10 MHz)

Vapsr *2 100 —

—

mVP–P

AVCC

Notes:

The specifications for parameters in this table are applicable only after any appropriate

stabilization time has elapsed.

1. The tsk(O) specification is only valid for equal loading of all outputs.

2. This parameter is characterized but not tested.

Timing requirements

Item

Symbol Min

Max

Unit

Test Conditions

Input clock frequency

Input clock duty cycle

f clock

50

40

125

MHz

60

%

Stabilization time *1

—

1

ms

After power up

Note:

1. Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its

reference signal. In order for phase lock to be obtained, a fixed-frequency, fixed-phase

reference signal must be present at CLK. Until phase lock is obtained, the specifications for

propagation delay and skew parameters given in the switching characteristics table are not

applicable.

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