74HC280 Просмотр технического описания (PDF) - STMicroelectronics

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74HC280

9-bit parity generator

STMicroelectronics 

M74HC280

9-bit parity generator

Datasheet - production data

SO14

TSSOP14

Features

• High-speed:

tPD = 22 ns (typ.) at VCC = 6 V

• Low power dissipation:

ICC = 4 μA (max.) at TA = 25 °C

• High noise immunity:

VNIH = VNIH = 28 % VCC (min)

• Symmetrical output impedance:

|IOH| = IOL = 4 mA (min.)

• Balanced propagation delays:

tPLH ≅ tPHL

• Wide operating voltage range:

VCC (opr) = 2 V to 6 V

• Pin and function compatible with 74 series 280

• ESD performance

– HBM: 2 kV

– MM: 200 V

– CDM: 1 kV

Description

The M74HC280 is a high-speed CMOS 9-bit

parity generator fabricated with silicon gate

C2MOS technology.

It is composed of nine data inputs (A to I) and

odd/even parity outputs (ΣODD and ΣEVEN). The

nine data inputs control the output conditions.

When the number of high-level inputs is odd,

ΣODD outputs are kept high and ΣEVEN outputs

are kept low. Conversely, when the number of

high-level outputs is even, ΣEVEN outputs are

kept high and ΣODD outputs are kept low. The IC

generates either odd or even parity making the

application flexible. The word-length capability is

easily expanded by cascading.

All inputs are equipped with protection circuits

against static discharge and transient excess

voltage.

Table 1. Device summary

Order code

Temp. range

Package

Packing

Marking

M74HC280RM13TR

M74HC280YRM13TR(1)

M74HC280TTR

M74HC280YTTR(1)

-55 °C to 125 °C

-40 °C to 125 °C

-55 °C to 125 °C

-40 °C to 125 °C

S014

SO14 (automotive grade)

TSSOP14

TSSOP14 (automotive grade)

Tape and reel

74HC280

74HC280Y

HC280

HC280Y

1. Qualification and characterization according to AEC Q100 and Q003 or equivalent, advanced screening according to AEC

Q001 and Q002 or equivalent.

January 2014

This is information on a product in full production.

DocID1938 Rev 2

1/14

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