RTC-4553 Просмотр технического описания (PDF) - Unspecified
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RTC-4553 Datasheet PDF : 2 Pages
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Real time clock module
Register table
Address
Register
A3 A2 A1 A0 symbol
D3
MODE 0
Counter control register
D2
D1
D0
Register name
MODE 1
User RAM Domain 1
D3
D2
D1
D0
MODE 2
User RAM Domain 2
D3
D2
D1
D0
0 00 0 0
S1
S8
S4
S2
S1 1-second digit register
RA3 RA2 RA1 RA0 RA63 RA62 RA61 RA60
1 00 0 1
S10
0
S40
S20
S10 10-second digit register
RA7 RA6 RA5 RA4 RA67 RA66 RA65 RA64
2 0 0 1 0 MI1
mi8
mi4
mi2
mi1 1-minute digit register
RA11 RA10 RA9 RA8 RA71 RA70 RA69 RA68
3 0 0 1 1 MI10
0
mi40
mi20
mi10 10-minute digit register
RA15 RA14 RA13 RA12 RA75 RA74 RA73 RA72
4 01 0 0
H1
h8
h4
h2
h1 1-hour digit register
RA19 RA18 RA17 RA16 RA79 RA78 RA77 RA76
5 0 1 0 1 H10
PM/AM
0
h20
h10 10-hour digit register
RA23 RA22 RA21 RA20 RA83 RA82 RA81 RA80
6 01 1 0 W
0
w4
w2
w1
Day of the week digit register RA27 RA26 RA25 RA24 RA87 RA86 RA85 RA84
7 01 1 1
D1
d8
d4
d2
d1 1-day digit register
RA31 RA30 RA29 RA28 RA91 RA90 RA89 RA88
8 1 0 0 0 D10
0
0
d20
d10 10-day digit register
RA35 RA34 RA33 RA32 RA95 RA94 RA93 RA92
9 1 0 0 1 MO1
mo8
mo4
mo2
mo1 1-month digit register
RA39 RA38 RA37 RA36 RA99 RA98 RA97 RA96
A 1 0 1 0 MO10
0
0
0
mo10 10-month digit register
RA43 RA42 RA41 RA40 RA103 RA102 RA101 RA100
B 10 1 1
Y1
y8
y4
y2
y1 1-year digit register
RA47 RA46 RA45 RA44 RA107 RA106 RA105 RA104
C 11 0 0
Y10
y80
y40
y20
y10 10-year digit register
RA51 RA50 RA49 RA48 RA111 RA110 RA109 RA108
D 11 0 1
C1
TPS 30ADJ CNTR 24/12 Control register 1
RA55 RA54 RA53 RA52 RA115 RA114 RA113 RA112
E 11 1 0
C2
BUSY PONC
—
∗
Control register 2
RA59 RA58 RA57 RA56 RA119 RA118 RA117 RA116
F 11 1 1
C3
SYSR TEST
MS1
MS0 Control register 3
Same as MODE 0
Same as MODE 0
Note: ∗ TEST bit should be “0”.
Switching characteristics (Ta=-30˚C to +70˚C, VDD=5V±10%, GND=OV)
Timing chart
Item
___
SCK input frequency
___
SCK “L” time
___
SCK “H” time
___
S_C_K pause time
C_S_0 setup time
CS0 hold time
Symbol Condition Min. Typ. Max. Unit
fSCK
—
500 kHz
tWSCKL
—
——
tWSCKH
1.0
tPS
tSCS
0
tHCS
0.5
µs
SIN data setup time
tSD
SIN data Hold time
tHD
___
WR setup time
tSWR
___
WR hold time
tHWR
—
—
0.2 —
1.0
0.5
__SOUT delay time
tDSO
__CS0, and CS1 enable to SOUT output tDSZ1
CS0 disenable to SOUT high Z
tDSZ2
CS1 enable to SOUT output
tDPZ1
150 500
CL=100pF — — 100
ns
CS1 enable to SOUT high Z
tDPZ2
CS 0
10%
SCK
SIN
WR
SOUT
CS0
90%
10%
tSCS
t WCKL
1/f CLK
10%
t SD
90%
10%
t DSZ1
t WCKH
90%
t HD
t SWR
90%
t HCS
t HWR
t DSZ2
SCK
Block diagram
32.768 kHz
Day
Sec. Min. Hou. of Day Mon. Year
t PS
OSC
Counter
Week
SCK
TPOUT
Output
control
Control Control Control
register register register
1
2
3
RAM
(120bit)
SOUT
10%
90%
10%
t DSO
SOUT
SCK
SIN
CS1
CS0
WR
Output control
Input
control
Shift register
Control circuit
CS1
TPOUT
90%
90%
10%
t DPZ1
10%
90%
10%
t DPZ2
48
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