RTC-4543SA Просмотр технического описания (PDF) - Unspecified
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RTC-4543SA Datasheet PDF : 2 Pages
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Register table
Real time clock module
MSB
Seconds (0 to 59)
FDT
s 40
s 20
s 10
s8
s4
s2
s1
Minutes (0 to 59)
∗
Hour (0 to 23)
∗
Day of the week (1 to 7)
Day (1 to 31)
∗
Month (1 to 12)
TM
mi 40
∗
∗
∗
mi 20
h 20
d 20
∗
mi 10
h 10
d 10
mo 10
mi 8
h8
∗
d8
mo 8
mi 4
h4
w4
d4
mo 4
mi 2
h2
w2
d2
mo 2
mi 1
h1
w1
d1
mo 1
year (0 to 99)
y 80
y 40
y 20
y 10
y8
y4
y2
y1
FDT bit: Supply voltage detection bit.
TM bit: Test bit always set this bit to "0".
Switching characteristics
(Ta=-40 to +85˚C, CL=30 pF)
Item
VDD= 5V± 10% VDD= 3V± 10%
Symbol
Unit
Min. Max. Min. Max.
CLK clock cycle
t CLK 0.75 7800
1.5 7800
CLK high pulse width
CLK low pulse width
CE setup time
t CLKH
t CLKL
3900
µs
3900
0.375
0.75
t CES
CE hold time
CE enable time
Write data setup time
Write data hold time
WR setup time
WR hold time
t CEH
—
—
t CE
—
0.9
—
0.9
s
t SD
0.1
t HD
—
0.2
µs
0.1
—
t WRS
100
100
ns
t WRH
DATA output delay time
t DATA
0.2
DATA output floating time
t DZ
0.1
0.4
µs
0.2
Clock input rise time
Clock input fall time
t r1
50
t f1
—
FOUT rise time
t r2
FOUT fall time
t f2
100
Disable time
CL= 30pF t XZ
100
—
ns
200
Enable time
FOUT duty ratio
t ZX
Duty 40
60
40
60
%
Wait time
t rcv
0.95
—
1.9
—
µs
Block diagram
32.768 kHz
FOUT
FSEL
FOE
DATA
CLK
WR
CE
Oscillator
Divider
Clock and calendar
Output
controller
Shift register
I/O
controller
Voltage
detecter
Control
circuit
Timing chart
Data read
WR
CE
CLK
DATA
tWRS
tCES
tCLK
tCLKH
tCLKL
tDATA
tCE
tr1 tf1
tWRH
tCEH
tRCV
tOZ
Data write
WR
CE
tWRS
tCLK
CLK
DATA
tCES
tCLKH
tCLKL
tSD tHD
FOUT
tf 2
tCE
tr1 tf1
tH
tCEH
tWRH
tRCV
FOUT
tr2
t
Disabled and Enabled
Duty=
tH
t
x
100
[%]
Enabled
FOE
VIH
Disabled
VIL
tXZ
tZX
FOUT
High impedance
50
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