RT9270 Просмотр технического описания (PDF) - Richtek Technology

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RT9270

High Performance, Low Noise Boost Converter

Richtek Technology 

Preliminary

RT9270

VRIPPLE = VRIPPLE(ESR) + VRIPPLE(C)

IPEAK VOUT - VIN

≅ IPEAK × ESRCOUT +

(

)

COUT VOUT × fOSC

Output Voltage

The regulated output voltage is calculated by :

R1

VOUT = 1.24V × (1+ )

R2

For most applications, R2 is a suggested a value up to

100kΩ. Place the resistor-divider as close to the IC as

possible to reduce the noise sensitivity.

Loop Compensation

The RT9270 voltage feedback loop can be compensated

with an external compensation network consisted of R3,

C3 and C4 (As shown in Figure 1). Choose R3 to set the

high-frequency integrator gain for fast transient response

without over or under compensation. Once R3 is

determined, C3 is selected to set the integrator zero to

maintain loop stability. The purpose of C4 is to cancel the

zero caused by output capacitor and the capacitor ESR.

If the ceramic capacitor is selected to be the output

capacitor, C4 can be taken off because of the small ESR.

C2 is the output capacitor as shown in Figure 1. The

following equations give approximate calculations of each

component :

C3 = 2 ×10-12 (F)

C2 × RL

Soft-Start Capacitor

The soft-start function begins from VSS=0V to VSS=1.24V

with a 4uA constant current charging to the soft-start

capacitor, so the capacitor should be large enough to let

the output voltage reach regulation inside the soft-start

cycle. Typical value of soft-start capacitor range is from

10nF to 200nF. After the cycle finished, the load can start

to draw maximum current as required.

Layout Guideline

For high frequency switching power supplies, the PCB

layout is important step in system application design. In

order to let IC achieve good regulation, high efficiency

and stability, it is strongly recommended the power

components should be placed as close as possible. These

traces should be wide and short. The feedback pin and

the networks of feedback and compensation should be

kept away from the power loops, and be shielded with a

ground trace or plane to prevent noise coupling.

VO × L1× C2

R3 =

(Ω)

2 × C3 × VIN

C4 = C2 × RESR ×1×10-6 (F)

The best criterion to optimize the loop compensation is

by inspecting the transient response and adjusting the

compensation network.

DS9270-09 March 2007

www.richtek.com

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