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RT9645

5 Channels ACPI Regulator

Richtek Technology 

RT9645

Preliminary

To prevent OC form tripping in normal operation, ROCSET

must be carefully chosen with :

1. Maximum RDS(ON) at highest junction temperature

2. Minimum IOCSET from specification table

3. IL(MAX) > IOUT(MAX) + Δ IL / 2

ΔIL = inductor ripple current

If Low side MOSFET with RDS(ON) = 6mΩ is used, the

OCP threshold current is about 20A. Once OCP is

triggered, the RT9645 enters S5 sleep state.

UGATE

(20V/Div)

LGATE

(10V/Div)

VOUT

(1V/Div)

ILOAD

(10A/Div)

Time (250μs/Div)

Figure 6. Over Cuuent Protection

Feedback Compensation

Figure 7 highlights the voltage-mode control loop for a

synchronous buck converter. Figure 8 shows the

corresponding Bode plot. The output voltage (VOUT) is

regulated to the reference voltage. The error amplifier EA

output (COMP) is compared with the oscillator (OSC)

sawtooth wave to provide a pulse-width modulated (PWM)

wave with an amplitude of VIN at the PHASE node. The

PWM wave is smoothed by the output filter (L and COUT).

The modulator transfer function is the small-signal transfer

function of VOUT/COMP. This function is dominated by a

DC gain and the output filter (L and COUT), with a double

pole break frequency at FP_LC and a zero at FZ_ESR. The

DC gain of the modulator is simply the input voltage (VIN)

divided by the peak-to-peak oscillator voltage ΔVOSC. The

break frequency FLC and FESR are expressed as Equation

(1) and (2) respectively.

FP _ LC = 2π

1

LCOUT

(1)

FZ _ ESR

=

1

2π × ESR × COUT

(2)

The compensation network consists of the error amplifier

EA and the impedance networks ZIN and ZFB. The goal of

the compensation network is to provide a closed loop

transfer function with the highest DC gain, the highest

0dB crossing frequency (FC) and adequate phase margin.

Typically, FC in range 1/5 to 1/10 of switching frequency

is adequate. Higher FC will cause faster dynamic

response. A phase margin in the range of 45°C to 60°C is

desirable. The equations below relate the compensation

network poles, zeros and gain to the components (R1,

R2, R3, C1, C2, and C3) in Figure 7.

FZ1

=

1

2π × R2 ×

C1

(3)

FZ2

=

1

2π × (R1+ R3) × C3

(4)

FP1

=

1

2π

×

R2

×

C1×

C1+

C2

C2

(5)

FP2

=

1

2π × R3 × C3

(6)

OSC

PWM

Comparator

-

ΔVOSC

+

VIN

Driver

Driver

L

PHASE

COUT

VOUT

ZFB

VE/A

-

EA+

ZIN

REF

ESR

C2

ZFB

C1 R2

C3

ZIN VOUT

R3

COMP

-

FB

EA

+

REF

R1

RFB

Figure 7

www.richtek.com

10

DS9645-00 August 2007

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