RT9218B Просмотр технического описания (PDF) - Richtek Technology

Номер в каталоге

Компоненты Описание

Список матч

RT9218B

12V Synchronous Buck PWM DC-DC and Linear Power Controller

Richtek Technology 

RT9218B

The AC impedance of output capacitor at operating

frequency is quite smaller than the load impedance, so

the ripple current (ΔIL) of the inductor current flows mainly

through output capacitor. The output ripple voltage is

described as :

ΔVOUT = ΔVOR + ΔVOC

(2)

ΔVOUT

=

ΔIL

× rc

+

1

CO

∫ t2

t1

ic

dt

(3)

ΔVOUT

=

ΔIL

× ΔIL

× rc

+

1

8

VOUT

COL

(1− D)T 2

S

(4)

where ΔVOR is caused by ESR and ΔVOC by capacitance.

For electrolytic capacitor application, typically 90 to 95%

of the output voltage ripple is contributed by the ESR of

output capacitor. So Equation (4) could be simplified as :

ΔVOUT = ΔIL x rc

(5)

Users could connect capacitors in parallel to get calculated

ESR.

Input Capacitor

The selection of input capacitor is mainly based on its

maximum ripple current capability. The buck converter

draws pulsewise current from the input capacitor during

the on time of S1 as shown in Figure 1. The RMS value of

ripple current flowing through the input capacitor is

described as :

Irms = IOUT D(1− D) (A)

(6)

The input capacitor must be cable of handling this ripple

current. Sometime, for higher efficiency the low ESR

capacitor is necessarily.

PWM Loop Stability

RT9218B is a voltage mode buck converter using the high

gain error amplifier with transconductance (OTA,

Operational Transconductance Amplifier).

The transconductance :

GM = dIOUT

dVm

The mid-frequency gain :

dVOUT = dIOUT ZOUT = GMdVINZOUT

G = dVOUT

dVIN

= GMZOUT

ZOUT is the shut impedance at the output node to ground

(see Figure 3 and Figure 4),

GM

VOUT

C1

C2

R1

Figure 3. A Type 2 error-amplifier with shut network to

ground

EA+ +

EA- - GM

+

RO

VOUT

Figure 4. Equivalent circuit

Pole and Zero :

FP

=

2π

1

× R1C2

;

FZ

=

2π

1

× R1C1

We can see the open loop gain and the Figure 3 whole

loop gain in Figure 5.

Open Loop, Unloaded Gain

A

Closed Loop, Unloaded Gain

FZ

FP

Gain = GMR1

B

100 1000 10k 100k

Frequency (Hz)

Figure 5. Gain with the Figure 2 circuit

RT9218B internal compensation loop :

GM = 0.2ms, R1 = 75kΩ, C1 = 2.5nF, C2 = 10pF

www.richtek.com

10

DS9218B-09 March 2007

Share Link: