RT9173B Просмотр технического описания (PDF) - Richtek Technology

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RT9173B

2A Bus Termination Regulator

Richtek Technology 

RT9173B

Note 1. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.

These are stress ratings only, and functional operation of the device at these or any other conditions beyond those

indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect device reliability.

Note 2. Devices are ESD sensitive. Handling precaution recommended. The human body model is a 100pF capacitor discharged

through a 1.5kΩ resistor into each pin.

Note 3. The device is not guaranteed to function outside its operating conditions.

Note 4. VOS offset is the voltage measurement defined as VOUT subtracted from VREFEN.

Note 5. θJA is measured in the natural convection at TA = 25°C on a low effective thermal conductivity test board of

JEDEC 51-3 thermal measurement standard. The case point of θJC is on the center of VCTRL pins (Lead 6 & 7) for

SOP-8 packages.

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DS9173B-09 March 2007

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