HM62G18512BP-5 Просмотр технического описания (PDF) - Hitachi -> Renesas Electronics
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HM62G18512BP-5 Datasheet PDF : 23 Pages
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Pin Description
Name
VDD
VSS
VDDQ
VREF
K
K
SS
SWE
SAn
SWEx
G
ZZ
ZQ
DQxn
I/O type
Supply
Supply
Supply
Supply
Input
Input
Input
Input
Input
Input
Input
Input
Input
I/O
M1, M2
TMS
TCK
TDI
TDO
NC
Input
Input
Input
Input
Output
—
HM62G18512 Series
Descriptions
Core power supply
Ground
Output power supply
Input reference: provides input reference voltage
Clock input. Active high.
Clock input. Active low.
Synchronous chip select
Synchronous write enable
Synchronous address input
Synchronous byte write enables
Asynchronous output enable
Power down mode select
Output impedance control
Synchronous data input/output
Output protocol mode select
Boundary scan test mode select
Boundary scan test clock
Boundary scan test data input
Boundary scan test data output
No connection
Notes
n = 0, 1, 2...18
x = a, b
1
x = a, b
n = 0, 1, 2...8
M1
M2
Protocol
Notes
VSS
VDD
Synchronous register to register operation
2
Notes: 1. ZQ is to be connected to VSS via a resistance RQ where 150 Ω ≤ RQ ≤ 300 Ω, if ZQ = VDDQ or
open, output buffer impedance will be maximum. A case of minimum impedance, it needs to
connect over 120 Ω between ZQ and VSS.
2. There is 1 protocol with mode pin. Mode control pins (M1, M2) are to be tied either VDD or VSS
respectively. The state of the Mode control inputs must be set before power-up and must not
change during device operation. Mode control inputs are not standard inputs and may not meet
VIH or VIL specification. This SRAM is tested only in the synchronous register to register
operation.
3
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