HM62G36256 Просмотр технического описания (PDF) - Hitachi -> Renesas Electronics
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HM62G36256 Datasheet PDF : 24 Pages
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HM62G36256 Series
Operation Table
ZZ SS G SWE SWEa SWEb SWEc SWEd K K Operation DQ (n) DQ (n + 1)
H× × ×
×
×
×
×
× × sleep mode High-Z
High-Z
L H× ×
×
×
×
×
L-H H-L Dead
×
(not selected)
High-Z
L × H×
×
×
×
×
× × Dead
High-Z High-Z
(Dummy read)
LLLH
×
×
×
×
L-H H-L Read
×
Dout
(a,b,c,d)0-8
LL×L
L
L
L
L
L-H H-L Write a, b, c, d High-Z Din (a,b,c,d)0-8
byte
LL×L
H
L
L
L
L-H H-L Write b, c, d High-Z Din (b,c,d)0-8
byte
LL×L
L
H
L
L
L-H H-L Write a, c, d High-Z Din (a,c,d)0-8
byte
LL×L
L
L
H
L
L-H H-L Write a, b, d High-Z Din (a,b,d)0-8
byte
LL×L
L
L
L
H
L-H H-L Write a, b, c High-Z
Din (a,b,c)0-8
byte
LL×L
H
H
L
L
L-H H-L Write c, d byte High-Z Din (c,d)0-8
LL×L
L
H
H
L
L-H H-L Write a, d byte High-Z Din (a,d)0-8
LL×L
L
L
H
H
L-H H-L Write a, b byte High-Z
Din (a,b)0-8
LL×L
H
L
L
H
L-H H-L Write b, c byte High-Z
Din (b,c)0-8
LL×L
H
H
H
L
L-H H-L Write d byte High-Z Din (d)0-8
LL×L
H
H
L
H
L-H H-L Write c byte High-Z
Din (c)0-8
LL×L
H
L
H
H
L-H H-L Write b byte High-Z
Din (b)0-8
LL×L
L
H
H
H
L-H H-L Write a byte High-Z
Din (a)0-8
Notes: 1. × means don’t care for synchronous inputs, and H or L for asynchronous inputs.
2. SWE, SS, SWEa to SWEd, SA are sampled at the rising edge of K clock.
3. Although differential clock operation is implied, this SRAM will operate properly with one clock
phase (either K or K) tied to VREF. Under such single-ended clock operation, all parameters
specified within this document will be met.
5
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