HM62G36256BP-4 Просмотр технического описания (PDF) - Hitachi -> Renesas Electronics

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HM62G36256BP-4

8M Synchronous Fast Static RAM (256k-word × 36-bit)

Hitachi -> Renesas Electronics 

HM62G36256 Series

Boundary Scan Test Access Port Operations

In order to perform the interconnect testing of the modules that include this SRAM, the serial boundary

scan test access port (TAP) is designed to operate in a manner consistent with IEEE Standard 1149.1 -

1990. But does not implement all of the functions required for 1149.1 compliance The HM62Gxx series

contains a TAP controller. Instruction register, Boundary scans register, Bypass register and ID register.

Test Access Port Pins

Symbol I/O

Name

TCK

Test clock

TMS

Test mode select

TDI

Test data in

TDO

Test data out

Note: This Device does not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1.

To disable the TAP, TCK must be connected to VSS. TDO should be left unconnected.

To test Boundary scan, ZZ pin need to be kept below VREF – 0.4 V.

TAP DC Operating Conditions (Ta = 0 to 70°C, [Tj max = 110°C])

Parameter

Boundary scan input high voltage

Boundary scan input low voltage

Boundary scan input leakage current

Boundary scan output low voltage

Boundary scan output high voltage

Notes: 1. 0 ≤ Vin ≤ VDD for all logic input pin.

2. IOL = 8 mA.

3. IOH = –8 mA.

Symbol

VIH

VIL

I LI

VOL

VOH

Min

2.0

–0.5

–2

—

2.4

Max

Unit

VDD + 0.3 V

0.8

V

2

µA

0.4

V

—

V

Notes

1

2

3

16

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