RT9006A Просмотр технического описания (PDF) - Richtek Technology
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RT9006A Datasheet PDF : 10 Pages
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RT9006A/B
Application Information
Detector Delay Time
The delay time (Td) of Reset signal from VOUT2 can be
calculated from the formula :
Td = CCT x 0.8 x VIN2
I CT
VIN2 is the input voltage of channel 2 and the ICT(2.6uA.Typ.)
is the CT pin sourcing current. CCT is the capacitance of
the external capacitor from CT pin to GND.
Current limit
The RT9006 contains two independent current limiters,
which monitors and controls the pass transistor’ s gate
voltage, limiting the output current to a certain level. The
typical current limit level of channel 1 and channel 2 is
450mA and 600mA respectively.
Thermal Consideration
For continued operation, do not exceed absolute maximum
operation junction temperature 125°C. The maximum power
dissipation depends on the thermal resistance of IC
package, PCB layout, the rate of surroundings airflow and
temperature difference between junction to ambient. The
maximum power dissipation can be calculated by following
formula :
PD(MAX) = ( TJ(MAX) − TA ) / θJA
Where
TJ(MAX) : The maximum operation junction temperature
125°C.
TA : The operated ambient temperature.
θJA : The junction to ambient thermal resistance.
The junction to ambient thermal resistance for SOP-8
(Exposed Pad) package is 75°C/W on the standard
JEDEC 51-7 (4 layers, 2S2P) thermal test board. The
copper thickness is 2oz. The maximum power dissipation
at TA = 25°C can be calculated by following formula :
PD(MAX) = (125°C − 25°C) / 75 °C/W = 1.33W {SOP-8
(Exposed Pad) packages}
The maximum power dissipation depends on operating
ambient temperature for fixed TJ(MAX) and thermal resistance
θJA. For SOP-8 (Exposed Pad) packages, the Figure 1 of
de-rating curves allows the designer to see the effect of
rising ambient temperature on the maximum power allowed.
2.2
4-Layers PCB
2
1.8
1.6
1.4
1.2
Copper Area
1 70mm2
0.8 50mm2
0.6 30mm2
0.4 10mm2
0.2 Min. layout
0
0 16.25 32.5 48.75 65 81.25 97.5 113.8 130
Ambient Temperature (°C)
Figure 1. Derating Curves for SOP-8 (Exposed Pad)
Package
PCB Layout Considerations
The thermal resistance θJA of SOP-8 (Exposed Pad) is
determined by the package design and the PCB design.
However, the package design had been designed. If
possible, it's useful to increase thermal performance by
the PCB design. The thermal resistance θJA can be
decreased by adding a copper under the exposed pad of
SOP-8 (Exposed Pad) package.
As shown in Figure 2, the amount of copper area to which
the SOP-8 (Exposed Pad) is mounted affects thermal
performance. When mounted to the standard SOP-8
(Exposed Pad) pad (Figure 2.a), θJA is 75°C/W. Adding
copper area of pad under the SOP-8 (Exposed Pad)
(Figure 2.b) reduces the θJA to 64°C/W. Even further,
increasing the copper area of pad to 70mm2 (Figure 2.e)
reduces the θJA to 49°C/W.
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8
DS9006A/B-05 September 2007
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