RT8015APQW Просмотр технического описания (PDF) - Richtek Technology
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производитель
RT8015APQW Datasheet PDF : 14 Pages
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Function Block Diagram
SHDN/RT
SD
COMP
0.8V
EA
FB
OSC
Output
Clamp
Slope
Com
ISEN
OC
Limit
RT8015A
PVDD
Int-SS
POR
0.9V
0.7V
0.4V
Control
Logic
Driver
NISEN
NMOS I Limit
LX
PGND
VREF OTP
GND
VDD
Layout Guide
CIN must be placed between VDD
Output capacitor must be
and GND as closer as possible
near RT8015A
VIN
GND
CIN
COUT
VOUT LX should be
connected to Inductor
by wide and short
trace, keep sensitive
RT8015A
L1 components away
from this trace
CF R1 R2
PVDD 6
PVDD 7
VDD 8
FB 9
COMP 10
RCOMP
5 PGND
4 LX
3 LX
2 GND
1 SHDN/RT
ROSC
VOUT
CCOMP
GND
Connect the FB pin directly to feedback resistors. The
resistor divider must be connected between VOUT and GND.
DS8015A-04 March 2011
www.richtek.com
3
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