CY7C4811-15AC(1997) Просмотр технического описания (PDF) - Cypress Semiconductor

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Компоненты Описание

производитель

CY7C4811-15AC
(Rev.:1997)

256/512/1K/2K/4K/8K x9 x2 Double Sync™ FIFOs

Cypress Semiconductor 

CY7C4801/4811/4821

CY7C4831/4841/4851

Switching Waveforms (continued)

Reset Timing[12]

tRS

RSA(RSB)

RENA1, RENA2

(RENB1,RENB2)

tRSS

tRSS

tRSR

tRSR

WENA1

(WENB1)

tRSS

tRSR

WENA2/LDA

[14]

(WENB2/LDB)

EFA, PAEA

(EFB, PAEB)

FFA, PAFA

(FFB, PAFB)

QA0−QA8

(QB0−QB8)

tRSF

tRSF

tRSF

[13]

OEA(OEB)=1

OEA(OEB)=0

48X1–8

Notes:

12. The clocks (RCLKA,RCLKB, WCLKA,WCLKB) can be free-running during reset.

13. After reset, the outputs will be LOW if (OEA,OEB) = 0 and three-state if (OEA,OEB)=1.

14. Holding (WENA2/LDA,WENB2/LDB) HIGH during reset will make the pin act as a second enable pin. Holding(WENA2/LDA,WENB2/LDB) LOW during reset will make the

pin act as a load enable for the programmable flag offset registers.

Document #: 38-06005 Rev. **

Page 8 of 23

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